Pipelined architecture analog-to-digital converters (ADCs) have become the architecture of choice for high speed and moderate to high resolution devices. Subsequently, different techniques of the fault diagnosis by built in self-test (BIST) system have been developed. This book gives a rigorous, theoretical and mathematical analysis for the design of pipelined ADCs, along with detailed practical aspects of implementing it in very large-scale integration (VLSI). In each chapter a unique fault diagnosis technique for pipelined ADC has been proposed. Chapter 1 discusses a 1.8V 10-bit 500 mega samples-per-second parallel pipelined ADC, describing the design of high speed, low power, low voltage ADC in CMOS technology. Chapter 2 introduces a BIST system where both the circuit and its diagnosis tool are implemented on the same chip. Chapter 3 examines the design of an oscillation-based BIST system for a 1.8V 8-bit 125-mega samples per second pipelined ADC. Chapter 4 focuses on the evaluation of dynamic parameters of a pipelined ADC with an oscillation-based BIST. Chapter 5 covers reconfigurable BIST architecture for pipelined ADCs. The book is an ideal reference for graduate students and researchers within electrical, electronics and computer engineering.

Pipelined analog to digital converters (ADCs) have become the architecture of choice for high-speed and moderate- to high-resolution devices. Subsequently, different techniques of fault diagnosis by the built-in self-test (BIST) system have been developed. An ideal reference for graduate students and researchers within electrical, electronics and computer engineering, this book provides a rigorous, theoretical and mathematical analysis for the design of pipelined ADCs, along with detailed practical aspects of implementing it in very large-scale integration (VLSI). In each chapter a unique fault diagnosis technique for pipelined ADC has been proposed.

This project is a fault diagnosis and redesign effort for an 8-bit 20-MS/s pipelined analog-to-digital converter designed and fabricated in a 0.5 (micro)m CMOS process technology. This integrated circuit was designed using a 1.5 bit/stage pipelined architecture and uses seven stages, which forms the most critical part of the chip referred to as the 'pipeline core'. From the information received from the advisors of the previous team, the comparator included an adjustable reset time design-for-test (DFT) feature, but test results indicated minimal adjust range of the reset time.My part of this project was focused on the diagnosis and redesign of the comparator located within the Sub-ADC of the pipeline core.

Sixty-two proceedings papers and eight panel sessions from the April 1997 symposium exploring the difficulties inherent in testing electronic systems and providing innovative solutions to those problems. The papers span the key testing areas such as core and processor testing, delay test and diagnosis, RAM testing, BIST, scan and boundary scan, current testing (IDDQ), analog and mixed signal testing, verification, and debugging. Additionally, new emerging processes were presented, describing thermal and elevated voltage tests, and power dissipation during test. Lacks an index. Annotation copyrighted by Book News, Inc., Portland, OR.