Introduction of monolithic inter-tier via (MIV) has opened new possibilities in three-dimensional (3D) VLSI design techniques. In this thesis, we propose a non-slicing 3-D floorplan representation to design block-level monolithic 3-D ICs. The new 3-D floorplan representation applied to simulated annealing-based optimization achieves smaller volume, shorter wire length, and lower dynamic power consumption than the Sequence Triple, Sequence Quintuple, and Slicing Tree 3-D floorplanning representations. The smaller size and reduced parasitics of MIV compared to through-silicon via (TSV) make designing cache memory in 3D a good choice. 3D cache memory is expected to achieve better performance with the number of layers increases. In this thesis, we explore different 3D memory design techniques and compare their power, delay, footprint, and energy-delay-product (EDP) values. First, we propose a new design methodology named Compact that consumes less power, incurs smaller delay and overall, shows better EDP compared to traditional 3D memory design techniques. Then we propose a new three-dimensional computer architecture to reduce context switch overhead.

This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration.

This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

Explore heterogeneous circuit integration and the packaging needed for practical applications of microsystems MEMS and system integration are important building blocks for the “More-Than-Moore” paradigm described in the International Technology Roadmap for Semiconductors. And, in 3D and Circuit Integration of MEMS, distinguished editor Dr. Masayoshi Esashi delivers a comprehensive and systematic exploration of the technologies for microsystem packaging and heterogeneous integration. The book focuses on the silicon MEMS that have been used extensively and the technologies surrounding system integration. You’ll learn about topics as varied as bulk micromachining, surface micromachining, CMOS-MEMS, wafer interconnection, wafer bonding, and sealing. Highly relevant for researchers involved in microsystem technologies, the book is also ideal for anyone working in the microsystems industry. It demonstrates the key technologies that will assist researchers and professionals deal with current and future application bottlenecks. Readers will also benefit from the inclusion of: A thorough introduction to enhanced bulk micromachining on MIS process, including pressure sensor fabrication and the extension of MIS process for various advanced MEMS devices An exploration of epitaxial poly Si surface micromachining, including process condition of epi-poly Si, and MEMS devices using epi-poly Si Practical discussions of Poly SiGe surface micromachining, including SiGe deposition and LP CVD polycrystalline SiGe A concise treatment of heterogeneously integrated aluminum nitride MEMS resonators and filters Perfect for materials scientists, electronics engineers, and electrical and mechanical engineers, 3D and Circuit Integration of MEMS will also earn a place in the libraries of semiconductor physicists seeking a one-stop reference for circuit integration and the practical application of microsystems.

The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising Moore-like exponential growth sustainable through to the 2030s.