Explains current co-design and co-optimization methodologies for building hardware neural networks and algorithms for machine learning applications This book focuses on how to build energy-efficient hardware for neural networks with learning capabilities—and provides co-design and co-optimization methodologies for building hardware neural networks that can learn. Presenting a complete picture from high-level algorithm to low-level implementation details, Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design also covers many fundamentals and essentials in neural networks (e.g., deep learning), as well as hardware implementation of neural networks. The book begins with an overview of neural networks. It then discusses algorithms for utilizing and training rate-based artificial neural networks. Next comes an introduction to various options for executing neural networks, ranging from general-purpose processors to specialized hardware, from digital accelerator to analog accelerator. A design example on building energy-efficient accelerator for adaptive dynamic programming with neural networks is also presented. An examination of fundamental concepts and popular learning algorithms for spiking neural networks follows that, along with a look at the hardware for spiking neural networks. Then comes a chapter offering readers three design examples (two of which are based on conventional CMOS, and one on emerging nanotechnology) to implement the learning algorithm found in the previous chapter. The book concludes with an outlook on the future of neural network hardware. Includes cross-layer survey of hardware accelerators for neuromorphic algorithms Covers the co-design of architecture and algorithms with emerging devices for much-improved computing efficiency Focuses on the co-design of algorithms and hardware, which is especially critical for using emerging devices, such as traditional memristors or diffusive memristors, for neuromorphic computing Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design is an ideal resource for researchers, scientists, software engineers, and hardware engineers dealing with the ever-increasing requirement on power consumption and response time. It is also excellent for teaching and training undergraduate and graduate students about the latest generation neural networks with powerful learning capabilities.

Brain Tumor MRI Image Segmentation Using Deep Learning Techniques offers a description of deep learning approaches used for the segmentation of brain tumors. The book demonstrates core concepts of deep learning algorithms by using diagrams, data tables and examples to illustrate brain tumor segmentation. After introducing basic concepts of deep learning-based brain tumor segmentation, sections cover techniques for modeling, segmentation and properties. A focus is placed on the application of different types of convolutional neural networks, like single path, multi path, fully convolutional network, cascade convolutional neural networks, Long Short-Term Memory - Recurrent Neural Network and Gated Recurrent Units, and more. The book also highlights how the use of deep neural networks can address new questions and protocols, as well as improve upon existing challenges in brain tumor segmentation. - Provides readers with an understanding of deep learning-based approaches in the field of brain tumor segmentation, including preprocessing techniques - Integrates recent advancements in the field, including the transformation of low-resolution brain tumor images into super-resolution images using deep learning-based methods, single path Convolutional Neural Network based brain tumor segmentation, and much more - Includes coverage of Long Short-Term Memory (LSTM) based Recurrent Neural Network (RNN), Gated Recurrent Units (GRU) based Recurrent Neural Network (RNN), Generative Adversarial Networks (GAN), Auto Encoder based brain tumor segmentation, and Ensemble deep learning Model based brain tumor segmentation - Covers research Issues and the future of deep learning-based brain tumor segmentation

Nanoscale devices attracted significant research effort from the industry and academia due to their operation principals being based on different physical properties which provide advantages in the design of certain classes of circuits over conventional CMOS transistors. Neuromorphic Circuits for Nanoscale Devices contains recent research papers presented in various international conferences and journals to provide insight into how the operational principles of the nanoscale devices can be utilized for the design of neuromorphic circuits for various applications of non-volatile memory, neural network training/learning, and image processing. The topics discussed in the book include:Nanoscale Crossbar Memory DesignQ-Learning and Value Iteration using Nanoscale DevicesImage Processing and Computer Vision Applications for Nanoscale DevicesNanoscale Devices based Cellular Nonlinear/Neural Networks

This open access book presents an overview of recent advances in photonic neural networks with spatiotemporal dynamics. The computing and implementation paradigms presented in this book are outcomes of interdisciplinary studies by collaborative researchers from the three fields of nonlinear mathematical science, information photonics, and integrated systems engineering. This book offers novel multidisciplinary viewpoints on photonic neural networks, illustrating recent advances in three types of computing methodologies: fluorescence energy transfer computing, spatial-photonic spin system, and photonic reservoir computing. The book consists of four parts: Part I introduces the backgrounds of optical computing and neural network dynamics; Part II presents fluorescence energy transfer computing, a novel computing technology based on nanoscale networks of fluorescent particles; Parts III and IV review the models and implementation of spatial-photonic spin systems and photonic reservoir computing, respectively. These contents are beneficial to researchers in a broad range of fields, including information science, mathematical science, applied physics, and engineering, to better understand the novel computing concepts of photonic neural networks with spatiotemporal dynamics.

This book provides a structured treatment of the key principles and techniques for enabling efficient processing of deep neural networks (DNNs). DNNs are currently widely used for many artificial intelligence (AI) applications, including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Therefore, techniques that enable efficient processing of deep neural networks to improve key metrics—such as energy-efficiency, throughput, and latency—without sacrificing accuracy or increasing hardware costs are critical to enabling the wide deployment of DNNs in AI systems. The book includes background on DNN processing; a description and taxonomy of hardware architectural approaches for designing DNN accelerators; key metrics for evaluating and comparing different designs; features of DNN processing that are amenable to hardware/algorithm co-design to improve energy efficiency and throughput; and opportunities for applying new technologies. Readers will find a structured introduction to the field as well as formalization and organization of key concepts from contemporary work that provide insights that may spark new ideas.

This book presents recent advances towards the goal of enabling efficient implementation of machine learning models on resource-constrained systems, covering different application domains. The focus is on presenting interesting and new use cases of applying machine learning to innovative application domains, exploring the efficient hardware design of efficient machine learning accelerators, memory optimization techniques, illustrating model compression and neural architecture search techniques for energy-efficient and fast execution on resource-constrained hardware platforms, and understanding hardware-software codesign techniques for achieving even greater energy, reliability, and performance benefits.

Nanoscale devices attracted significant research effort from the industry and academia due to their operation principals being based on different physical properties which provide advantages in the design of certain classes of circuits over conventional CMOS transistors. Neuromorphic Circuits for Nanoscale Devices contains recent research papers presented in various international conferences and journals to provide insight into how the operational principles of the nanoscale devices can be utilized for the design of neuromorphic circuits for various applications of non-volatile memory, neural network training/learning, and image processing. The topics discussed in the book include: Nanoscale Crossbar Memory Design Q-Learning and Value Iteration using Nanoscale Devices Image Processing and Computer Vision Applications for Nanoscale Devices Nanoscale Devices based Cellular Nonlinear/Neural Networks

This book provides readers with an up-to-date account of the use of machine learning frameworks, methodologies, algorithms and techniques in the context of computer-aided design (CAD) for very-large-scale integrated circuits (VLSI). Coverage includes the various machine learning methods used in lithography, physical design, yield prediction, post-silicon performance analysis, reliability and failure analysis, power and thermal analysis, analog design, logic synthesis, verification, and neuromorphic design. Provides up-to-date information on machine learning in VLSI CAD for device modeling, layout verifications, yield prediction, post-silicon validation, and reliability; Discusses the use of machine learning techniques in the context of analog and digital synthesis; Demonstrates how to formulate VLSI CAD objectives as machine learning problems and provides a comprehensive treatment of their efficient solutions; Discusses the tradeoff between the cost of collecting data and prediction accuracy and provides a methodology for using prior data to reduce cost of data collection in the design, testing and validation of both analog and digital VLSI designs. From the Foreword As the semiconductor industry embraces the rising swell of cognitive systems and edge intelligence, this book could serve as a harbinger and example of the osmosis that will exist between our cognitive structures and methods, on the one hand, and the hardware architectures and technologies that will support them, on the other....As we transition from the computing era to the cognitive one, it behooves us to remember the success story of VLSI CAD and to earnestly seek the help of the invisible hand so that our future cognitive systems are used to design more powerful cognitive systems. This book is very much aligned with this on-going transition from computing to cognition, and it is with deep pleasure that I recommend it to all those who are actively engaged in this exciting transformation. Dr. Ruchir Puri, IBM Fellow, IBM Watson CTO & Chief Architect, IBM T. J. Watson Research Center