VHDL Answers to Frequently asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp. lang. vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error free, and simulation efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complete simulatable examples. TItis book is intended for those who are seeking an enhanced proficiency in VHDL. Its target audience includes: 1. Engineers. The book addresses a set of problems commonly experienced by real users of VHDL. It provides practical explanations to the questions, and suggests practical solutions to the raised issues. It also includes packages of common utilities that are useful in the generation of debug code and testbench designs. These packages include conversions to strings (the IMAGE package), generation of Linear Feedback Shift Registers (LFSR), Multiple Input Shift Register (MISR), and random number generators.

VHDL Coding Styles and Methodologies, Edition is a follow up book to the first edition of same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy to read book that gave in depth coverage of both, the language and coding methodologies. This edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD. The CD also includes the GNU toolsuite with EMACS language sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology graciously included a timed evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. In addition, Synplicity included a timed version of Synplify, a very efficient, user friendly and easy to use FPGA synthesis tool. Synplify provides a user both the RTL and gate level views of the synthesized model, and a performance report of the design. Optimization mechanisms are provided in the tool.

An eagerly anticipated, up-to-date guide to essential digital design fundamentals Offering a modern, updated approach to digital design, this much-needed book reviews basic design fundamentals before diving into specific details of design optimization. You begin with an examination of the low-levels of design, noting a clear distinction between design and gate-level minimization. The author then progresses to the key uses of digital design today, and how it is used to build high-performance alternatives to software. Offers a fresh, up-to-date approach to digital design, whereas most literature available is sorely outdated Progresses though low levels of design, making a clear distinction between design and gate-level minimization Addresses the various uses of digital design today Enables you to gain a clearer understanding of applying digital design to your life With this book by your side, you'll gain a better understanding of how to apply the material in the book to real-world scenarios.

This practical, tool-independent guide to designing digital circuits takes a unique, top-down approach, reflecting the nature of the design process in industry. Starting with architecture design, the book comprehensively explains the why and how of digital circuit design, using the physics designers need to know, and no more.

Fundamentals of Digital Logic With VHDL Design teaches the basic design techniques for logic circuits. It emphasizes the synthesis of circuits and explains how circuits are implemented in real chips. Fundamental concepts are illustrated by using small examples, which are easy to understand. Then, a modular approach is used to show how larger circuits are designed. VHDL is used to demonstrate how the basic building blocks and larger systems are defined in a hardware description language, producing designs that can be implemented with modern CAD tools. The book emphasizes the concepts that should be covered in an introductory course on logic design, focusing on: Logic functions, gates, and rules of Boolean algebra Circuit synthesis and optimization techniques Number representation and arithmetic circuits Combinational-circuit building blocks, such as multiplexers, decoders, encoders, and code converters Sequential-circuit building blocks, such as flip-flops, registers, and counters Design of synchronous sequential circuits Use of the basic building blocks in designing larger systems It also includes chapters that deal with important, but more advanced topics: Design of asynchronous sequential circuits Testing of logic circuits For students who have had no exposure to basic electronics, but are interested in learning a few key concepts, there is a chapter that presents the most basic aspects of electronic implementation of digital circuits. Major changes in the second edition of the book include new examples to clarify the presentation of fundamental concepts over 50 new examples of solved problems provided at the end of chapters NAND and NOR gates now introduced in Chapter 2 more complete discussion of techniques for minimization of logic functions in Chapter 4 (including the tabular method) a new chapter explaining the CAD flow for synthesis of logic circuits Altera's Quartus II CAD software provided on a CD-ROM three appendices that give tutorials on the use of Quartus II software

mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification.

CHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility Packages 231 VHDL Implementation 237 Packaging Bus-Functional Procedures 238 240 Creating a Test Harness 243 Abstracting the Client/Server Protocol Managing Control Signals 246 Multiple Server Instances 247 Utility Packages 249 Autonomous Generation and Monitoring 250 Autonomous Stimulus 250 Random Stimulus 253 Injecting Errors 255 Autonomous Monitoring 255 258 Autonomous Error Detection Input and Output Paths 258 Programmable Testbenches 259 Configuration Files 260 Concurrent Simulations 261 Compile-Time Configuration 262 Verifying Configurable Designs 263 Configurable Testbenches 265 Top Level Generics and Parameters 266 Summary 268 CHAPTER 7 Simulation Management 269 Behavioral Models 269 Behavioral versus Synthesizable Models 270 Example of Behavioral Modeling 271 Characteristics of a Behavioral Model 273 x Writing Testbenches: Functional Verification of HDL Models Modeling Reset 276 Writing Good Behavioral Models 281 Behavioral Models Are Faster 285 The Cost of Behavioral Models 286 The Benefits of Behavioral Models 286 Demonstrating Equivalence 289 Pass or Fail? 289 Managing Simulations 292 294 Configuration Management Verilog Configuration Management 295 VHDL Configuration Management 301 SDF Back-Annotation 305 Output File Management 309 Regression 312 Running Regressions 313 Regression Management 314 Summary 316 APPENDIX A Coding Guidelines 317 Directory Structure 318 VHDL Specific 320 Verilog Specific 320 General Coding Guidelines 321 Comments 321 Layout 323 Syntax 326 Debugging 329 Naming Guidelines 329 Capitalization 330 Identifiers 332 Constants 334 334 HDL Specific Filenames 336 HDL Coding Guidelines 336 337 Structure 337 Layout