This issue of ECS Transactions contains the peer-reviewed full length papers of the International Symposium on Silicon Nitride, Silicon Dioxide, and Emerging Dielectrics held May 1-6, 2011 in Montreal as a part of the 219th Meeting of The Electrochemical Society. The papers address a very diverse range of topics. In addition to the deposition and characterization of the dielectrics, more specific topics addressed by the papers include applications, device characterization and reliability, interface states, interface traps, defects, transistor and gate oxide studies, and modeling.

Over 50 years, Moore's law has successfully predicted the progress of the silicon electronics industry. However, Moore's law is approaching to the end recently, and new material and novel device type will be needed for next-generation devices. Two-dimensional (2D) layered material is one of the promising candidates due to its intrinsic desirable features, such as diverse electronic and magnetic properties, carrier mobility protection with decreasing body thickness, and flexibility for wearable applications. Furthermore, hetero-structure comprising of 2D crystals is of growing interest since various combinations are possible for multiple purposes as more and more van der Waals materials have been discovered. In a hetero-structure, electrons can propagate not only within 2D in-plane direction but also in the vertical out-of-plane direction. However, our understanding of the vertical carrier transport is greatly less than that on the lateral. Thus, using lateral electron energy band diagrams are still the main vehicle in 2D vertical hetero-structure device analysis, which may not be correct. In this dissertation, silicon-based tunneling devices were fabricated and used to investigate electron transport properties when electrons go into or go across a 2D materials with the measurement of electron tunneling spectroscopy. We firstly examine the role of 2D sheet when electrons propagate perpendicularly across it. Here graphene is used as a platform since it is the earliest discovered one, and it has the most mature development including understanding and growth techniques. Graphene together with its neighboring van de Waals gaps serves as a tunnel barrier and barely has interaction with the vertically tunneling electrons. However, since graphene can still trap a fraction of carriers, we can take advantage of it and control the carrier flux via the adjustment of graphene electrical potential. In addition to vertically propagating across a graphene sheet, electrons can go into graphene lateral band structure and transport within graphene. In chapter 3, we introduce a new model of the interfacial oscillation states at graphene-silicon hetero-junction, which is found and confirmed for the first time. Because of the presence of this discrete interfacial quantum state, Fano-Feshbach resonance is induced by its interaction with graphene's continuum lateral energy diagram. This study provided a further elucidation of the interfacial effect in a low-dimension materials based system. The capability of our silicon-based tunneling device along with electron tunneling spectroscopy is not limited to the graphene-silicon interface but also able to investigate electron in-plane transport behavior within 2D hetero-structure. Since large-size devices and their macroscopic characteristics would be needed for our everyday applications in the future, the strength of our tunneling device over the conventional scanning tunneling spectroscopy with a sharp tip is its scalable detecting area. Here, a study on graphene/hexagonal boron nitride hetero-stack prepared by chemical vapor deposition and large-area wet transfer techniques shows multiple secondary Dirac points and the preferred relative rotation angle of ~4 and ~7 . The theoretical calculation was also implemented to support our experimental observation. Raman spectroscopy and scanning tunneling microscope were carried out to confirm the Moire pattern formation. This study provides a useful way to macroscopically conduct research on the electronic behavior of a van der Waals material, and our findings may be used when graphene/hexagonal boron nitride hetero-structure is pushed to practical applications. Undoubtedly, further careful study is needed for more detailed verification.

Recent developments in the technology of silicon nanocrystals and silicon nanostructures, where quantum-size effects are important, are systematically described including examples of device applications. Due to the strong quantum confinement effect, the material properties are freed from the usual indirect- or direct-bandgap regime, and the optical, electrical, thermal, and chemical properties of these nanocrystalline and nanostructured semiconductors are drastically changed from those of bulk silicon. In addition to efficient visible luminescence, various other useful material functions are induced in nanocrystalline silicon and periodic silicon nanostructures. Some novel devices and applications, in fields such as photonics (electroluminescence diode, microcavity, and waveguide), electronics (single-electron device, spin transistor, nonvolatile memory, and ballistic electron emitter), acoustics, and biology, have been developed by the use of these quantum-induced functions in ways different from the conventional scaling principle for ULSI.

Presented here is an all-inclusive treatment of Flash technology, including Flash memory chips, Flash embedded in logic, binary cell Flash, and multilevel cell Flash. The book begins with a tutorial of elementary concepts to orient readers who are less familiar with the subject. Next, it covers all aspects and variations of Flash technology at a mature engineering level: basic device structures, principles of operation, related process technologies, circuit design, overall design tradeoffs, device testing, reliability, and applications.

Decreasing the size of transistor structures (“scaling”') is an ongoing trend in microelectronics, since smaller structures allow more chips to be placed on a wafer. So far, the result has always been a cost saving, with increasing complexity and clock frequency as welcome side effects. But shrinking the conventional MOSFET, on which the conventional CMOS technology is built on, leads to an increasing number of problems with every new technology generation. Many electrical parameters of the conventional MOSFET deteriorate by shrinking its channel length. The resulting short channel effects require ever more complicated compensation structures. Yet certain parameters such as the sub-threshold swing or the width of space charge regions do not scale. Thus, with decreasing channel length it becomes increasingly difficult to design a conventional MOSFET that can be switched off. Approaching approximately 10 nm, electrons would tunnel through the channel region even if the device was to be turned off, leading to unacceptable leakage currents. Instead of trying to avoid quantum mechanical tunneling, we could try to take advantage of it. This leads to the concept of the tunnel FET. It consists of a p-i-n diode, which has to be reverse-biased, and a gate stack like a conventional MOSFET. Its off-current is the leakage current of the p-i-n diode, which is extremely low and caused mainly by charge carrier generation in the intrinsic region. A positive gate voltage creates an electron-channel at the surface of the intrinsic region, which leads to a strong band bending at the p-end of the device. This allows electrons to tunnel from the valence band to the conduction band, resulting in a tunneling current. The same happens between the n-end of the device and a hole-channel caused by a negative gate voltage. The motivation for this work is the fact that this device concept of the tunnel FET has already been studied by different groups by means of computer simulations, which already improved the physical understanding of this novel concept. In addition, experimental prototypes have also been produced. However, their doping profiles do not meet the stringent demands, which have to be fulfilled in order to utilize the full potential of this device concept. Conventional CMOS technologies are insufficient, because the tunnel FET needs extremely sharp doping profiles, meaning very high concentration gradients. This is why the electrical characteristics of experimental prototypes have so far deviated significantly from computer simulations. This work focuses on the development of manufacturing processes for experimental prototypes, which show the required doping profiles. The main idea is to realize the tunnel FET vertically. First, the p-i-n layer stack was grown by epitaxy on a silicon substrate. Then freestanding mesa structures were created, by etching away all unnecessary parts of the p-i-n stack. This was followed by a gate stack; a passivation layer; and metal contacts. This method is already known from earlier work and is not applicable for mass production, but it has the important advantage that the channel length is determined by the epitaxy and can be controlled on a nanometer scale, despite the use of cheap photo lithography with a large minimum feature size. A serious problem of earlier investigations was the etching of the mesa structures; the achieved surface quality did not allow thin gate oxides. This resulted in a higher thermal budget, which led to a high diffusion of the doping atoms. Therefore a central aspect of this new work is: the development of a special dry-etch process for the necessary surface quality; the improvement of existing process steps; and the integration of new process modules into the device. In addition, the development of this process technology facilitated the production of SiGe tunnel FETs for the first time. The vertical transistor technology has been optimized to such an extent, that gate oxide thicknesses of less than 4 nm could be used and high surface mobilities could be achieved. This also revealed the limits of the vertical concept. Due to the high band gap of silicon, tunnel FETs made in silicon show an on-current which is far below industrial requirements. Any dopant diffusion reduces the on-current further. Simulations predict that the means of solving this problem could be the introduction of SiGe into the device, which is also a vital part of this work. However, this complicated the production of the gate stack for the vertical transistors, because the gate dielectric could not be grown by thermal oxidation and had to be replaced by an LPCVD silicon nitride The experimental prototypes built for this work confirmed most of the properties of the tunnel FET, which had been predicted by simulations. The drain current depends exponentially on the gate voltage. The spot-swing (a parameter similar to the subthreshold swing of a conventional MOSFET) depends on the gate voltage but not on temperature, and thus could be theoretically less than 60 mV/dec. The leakage currents are several orders of magnitudes below the ITRS requirements, and the output characteristics show perfect saturation independent of gate length. Since it is almost independent of temperature, the tunnel FET can be used above 120 °C with only minor changes of the electrical parameters, and thus at conditions which render the conventional MOSFET inoperable. The results obtained from the SiGe devices indicate that the on-current can be raised by orders of magnitude by using SiGe, as shown in simulations. However, further experiments will be necessary before any reliable conclusions can be drawn.

X-ray nanolithography for device fabrication was extended farther than previously reported. A new substrate photoelectron effect in x-ray nanolithography was observed. A way to circumvent this apparent limit to the resolution limits of x-ray nanolithography for real devices was found. Novel coulomb-blockade devices have been fabricated using this modified process. Preliminary measurements are underway on devices which should allow a better understanding of how the coulomb blockade disappears as coupling of the quantum dot to the environment increases via either a tunnel barrier or a quantum point contact.

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