Clock Distribution Network (CDN) is an important component of any synchronous logic circuit. The function of CDN is to deliver the clock signal to the clock sinks. Clock skew is defined as the difference in the arrival time of the clock signal at the clock sinks. Higher uncertainty in skew (due to PVT variations) degrades circuit performance by decreasing the maximum possible delay between any two sequential elements. Aggressive frequency scaling has also led to high power consumption especially in CDN. This dissertation addresses variation and power issues in the design of current and potential future CDN. The research detailed in this work presents algorithmic techniques for the following problems: (1) Variation tolerance in useful skew design, (2) Link insertion for buffered clock nets, (3) Methodology and algorithms for rotary clocking and (4) Clock mesh optimization for skew-power trade off. For clock trees this dissertation presents techniques to integrate the different aspects of clock tree synthesis (skew scheduling, abstract topology and layout embedding) into one framework- tolerance to variations. This research addresses the issues involved in inserting cross-links in a buffered clock tree and proposes design criteria to avoid the risk of short-circuit current. Rotary clocking is a promising new clocking scheme that consists of unterminated rings formed by differential transmission lines. Rotary clocking achieves reduction in power dissipation clock skew. This dissertation addresses the issues in adopting current CAD methodology to rotary clocks. Alternative methodology and corresponding algorithmic techniques are detailed. Clock mesh is a popular form of CDN used in high performance systems. The problem of simultaneous sizing and placement of mesh buffers in a clock mesh is addressed. The algorithms presented remove the edges from the clock mesh to trade off skew tolerance for low power. For clock trees as well as link insertion, our experiments indicate significant reduction in clock skew due to variations. For clock mesh, experimental results indicate 18.5% reduction in power with 1.3% delay penalty on a average. In summary, this dissertation details methodologies/algorithms that address two critical issues- variation and power dissipation in current and potential future CDN.

As VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield of VLSI circuits. Clock Distribution Network (CDN), which is one of the biggest and most important nets in any synchronous VLSI chip, is especially sensitive to these variations. To address this problem variability-aware analysis and optimization techniques for VLSI circuits are needed. In the first part of this thesis an analytical bound for the unwanted skew due to interconnect variation is established. Experimental results show that this bound is safer, tighter and computationally faster than existing approaches. This bound could be used in variation-aware clock tree synthesis. The second part of the thesis deals with optimizing a given clock tree to minimize the unwanted skew variations. Non-tree CDNs have been recognized as a promising approach to overcome the variation problem. We propose a novel non-tree CDN obtained by adding cross links in an existing clock tree. We analyze the effect of the link insertion on clock skew variability and propose link insertion schemes. The non-tree CDNs so obtained are shown to be highly tolerant to skew variability with very little increase in total wire-length. This can be used in applications such as ASIC design where a significant increase in the total wire-length is unacceptable.

A number of fundamental topics in the field of high performance clock distribution networks is covered in this book. High Performance Clock Distribution Networks is composed of ten contributions from authors at academic and industrial institutions. Topically, these contributions can be grouped within three primary areas. The first topic area deals with exploiting the localized nature of clock skew. The second topic area deals with the implementation of these clock distribution networks, while the third topic area considers more long-range aspects of next-generation clock distribution networks. High Performance Clock Distribution Networks presents a number of interesting strategies for designing and building high performance clock distribution networks. Many aspects of the ideas presented in these contributions are being developed and applied today in next-generation high-performance microprocessors.

Aggressive technology and clock frequency scaling have been key enablers to boosting integrated circuit (IC) performance over the last two decades. As technology scales further into the nanometer domain, maintaining the pace of multi-GHz clock frequency scaling and its associated performance enhancement has become challenging. This can be attributed primarily to the impact of variations introduced during IC fabrication, and the dynamic temperature-voltage changes during run-time. These variations can cause changes in wire and transistor delays, resulting in unpredictable performance differences between identical transistors on the same chip. As these variations increase with technology scaling, the clock cycle safety margin required to accommodate them also grow. This restricts the clock network from functioning at higher frequencies, resulting in limited system performance and throughput. This situation is further exacerbated by the rising clock network power consumption.^Clock network design techniques that increase clock frequency by enhancing robustness against variations also result in considerable power consumption, adding to the already large clock power. In the context of rapidly growing mobile and embedded battery powered applications, this presents a significant challenge for increasing system performance and extending battery life. The primary goal of this dissertation is to develop clock network design techniques that enhance its robustness against variations while ensuring minimum power consumption. In the first part of this dissertation, we examine the impact of variability on the clock distribution network (CDN). The impact of different sources of variations including random and systematic process variations, run-time temperature and supply voltage variations on CDN performance is analyzed through simulations in different technologies from 180nm to 45nm technologies.^Simulation results show the rapidly growing impact of interconnect variability in sub-65nm technologies. It also identifies parts of the CDN that contribute to the most clock delay variations, known as skew. These results help develop a new low area and power overhead clock deskewing technique to address interconnect variations and is targeted towards the skew-sensitive parts of the CDN to maximize effectiveness. In the second part, we develop a low-power robust clock network design technique that optimizes the CDN for power and robustness simultaneously, ensuring maximum robustness with minimal power consumption. To do this, we first model the impact of variations on buffered global interconnects, which form the CDNs. Through multiple regression analysis of buffered interconnects, we identify the variation-sensitive design parameters in the variability model and develop a power-robustness optimal design method for the buffered interconnect.^Next, we develop a metric to overcome the difficulty in using the statistical clock skew metric that is used in designing robust CDNs. The new metric based on the maximum clock path delay variance, developed using the variability model described above. The effectiveness of this metric in characterizing CDN robustness is shown using simulation results. We then extend the power-robustness optimal buffered interconnect design approach to designing all parts of the CDN while ensuring maximal robustness and minimum power consumption, as measured by the new metric. The enhanced CDN robustness achieved by the design techniques described above help reduce the clock network safety margins, resulting in higher clock frequencies and enhanced system performance while minimizing clock power consumption. The CDN variability modeling and optimal design approaches developed in this work can be extended to other parts of the system such as data path, memories and IO subsystems.^As an example, we have shown the application of this work to designing robust global interconnects that play an important role in intra-chip communication between different IPs and logic blocks.

. . . ????????????????????????????????? ????????????? ????????????,????? ???? ??????????? ???????????????????? ???. THUCYDIDIS HISTORIAE IV:108 C. Hude ed. , Teubner, Lipsiae MCMXIII ???????????,????? ??,? ????????????????? ???????????????????? ?????? ?????? ?????? ??? ????????? ??? ?’ ?????????? ??’ ?????????? ? ??????? ??? ????????????? ???????. ???????????????????:108 ???????????? ?????????????????????? ?. ?????????????. ????????????,????? It being the fashion of men, what they wish to be true to admit even upon an ungrounded hope, and what they wish not, with a magistral kind of arguing to reject. Thucydides (the Peloponnesian War Part I), IV:108 Thomas Hobbes Trans. , Sir W. Molesworth ed. In The English Works of Thomas Hobbes of Malmesbury, Vol. VIII I have been introduced to clock design very early in my professional career when I was tapped right out of school to design and implement the clock generation and distribution of the Alpha 21364 microprocessor. Traditionally, Alpha processors - hibited highly innovative clocking systems, always worthy of ISSCC/JSSC publi- tions and for a while Alpha processors were leading the industry in terms of clock performance. I had huge shoes to ?ll. Obviously, I was overwhelmed, confused and highly con?dent that I would drag the entire project down.

This text is intended for the undergraduate engineering students in Electrical and Electronics Engineering, Electronics and Communication Engineering, and Electronics and Instrumentation Engineering, and those pursuing postgraduate courses in Applied Electronics and VLSI Design. With the electronic devices and chips becoming smaller and smaller, the sizes of circuits and transistors on the microchips are approaching atomic levels. And so, Very Large-Scale Integration (VLSI) Design refers to the process of placing hundreds of thousands of electronic components on a single chip which nearly all modern computer architectures employ, and this technology has assumed a significant role in today’s tech savvy world. This well-organized, up-to-date and compact text explains the basic concepts of MOS technology including the fabrication methods, MOS characteristic behaviour, and design processes for layouts, etc. in a crisp and easy-to-learn style. The latest and most advanced techniques for maximising performance, minimising power consumption, and achieving rapid design turnarounds are discussed with great skill by the authors. Key Features  Gives an in-depth analysis of MOS structure, device characteristics, modelling and MOS device fabrication techniques.  Provides detailed description of CMOS design of combinatorial, sequential and arithmetic circuits with emphasis on practical applications.  Offers an insight into the CMOS testing techniques for the design of VLSI circuits.  Gives a number of solved problems in VHDL and Verilog languages.  Provides a number of short answer questions to help the students during examinations.

Logic optimization and clock network optimization for power, performance and area trade-off have been imperative problems for the very large scale integrated (VLSI) circuit designers. With further technology scaling, complex designs and aggressive time-to-market targets, scalable algorithms are very much anticipated than ever before. The logic optimizations can be at pre-synthesis stage, post-synthesis stage or even cross-layer. The success of the logic optimization is determined by how much it can benefit in metrics such as power and performance after physical placement and routing. Meanwhile, building a process variation tolerant and On-Chip-Variation (OCV) aware clock network to meet the performance/power target in modern designs has become an extremely difficult job, which calls for clock tree resynthesis, i.e., restructuring of an existing clock network, to achieve better power/performance. This dissertation first focuses on a pre-synthesis logic optimization problem, high performance adder synthesis. The optimization of the prefix network, capturing the carry-computation of any adder, has been shown to be effective even after logic synthesis, placement and routing over existing adder solutions, including even hand-made custom adders designed in industrial designs. Second a post-synthesis optimization problem, a new paradigm of discrete gate sizing under multiple operating conditions, is proposed to consider both system and logic level information. Besides it helps in design space exploration by providing feedback to the system level. Our paradigm is flexible to integrate various reliability and physical design issues. Finally, a clock network optimization problem, clock tree resynthesis, is proposed to achieve multi-corner, multi-mode timing closure and dynamic power minimization on an already synthesized and routed clock tree. The clock tree resynthesis algorithms have been integrated into an industrial placement and routing tool, and validated on large-scale industrial designs.