Every day, companies call upon their signal integrity engineers to make difficult decisions about design constraints and timing margins. Can I move these wires closer together? How many holes can I drill in this net? How far apart can I place these chips? Each design is unique: there’s no single recipe that answers all the questions. Today’s designs require ever greater precision, but design guides for specific digital interfaces are by nature conservative. Now, for the first time, there’s a complete guide to timing analysis and simulation that will help you manage the tradeoffs between signal integrity, performance, and cost. Writing from the perspective of a practicing SI engineer and team lead, Greg Edlund of IBM presents deep knowledge and quantitative techniques for making better decisions about digital interface design. Edlund shares his insights into how and why digital interfaces fail, revealing how fundamental sources of pathological effects can combine to create fault conditions. You won’t just learn Edlund’s expert techniques for avoiding failures: you’ll learn how to develop the right approach for your own projects and environment. Coverage includes • Systematically ensure that interfaces will operate with positive timing margin over the product’s lifetime–without incurring excess cost • Understand essential chip-to-chip timing concepts in the context of signal integrity • Collect the right information upfront, so you can analyze new designs more effectively • Review the circuits that store information in CMOS state machines–and how they fail • Learn how to time common-clock, source synchronous, and high-speed serial transfers • Thoroughly understand how interconnect electrical characteristics affect timing: propagation delay, impedance profile, crosstalk, resonances, and frequency-dependent loss • Model 3D discontinuities using electromagnetic field solvers • Walk through four case studies: coupled differential vias, land grid array connector, DDR2 memory data transfer, and PCI Express channel • Appendices present a refresher on SPICE modeling and a high-level conceptual framework for electromagnetic field behavior Objective, realistic, and practical, this is the signal integrity resource engineers have been searching for. Preface xiii Acknowledgments xvi About the Author xix About the Cover xx Chapter 1: Engineering Reliable Digital Interfaces 1 Chapter 2: Chip-to-Chip Timing 13 Chapter 3: Inside IO Circuits 39 Chapter 4: Modeling 3D Discontinuities 73 Chapter 5: Practical 3D Examples 101 Chapter 6: DDR2 Case Study 133 Chapter 7: PCI Express Case Study 175 Appendix A: A Short CMOS and SPICE Primer 209 Appendix B: A Stroll Through 3D Fields 219 Endnotes 233 Index 235

A Signal Integrity Engineer’s Companion Real-Time Test and Measurement and Design Simulation Geoff Lawday David Ireland Greg Edlund Foreword by Chris Edwards, Editor, IET Electronics Systems and Software magazine Prentice Hall Modern Semiconductor Design Series Prentice Hall Signal Integrity Library Use Real-World Test and Measurement Techniques to Systematically Eliminate Signal Integrity Problems This is the industry’s most comprehensive, authoritative, and practical guide to modern Signal Integrity (SI) test and measurement for high-speed digital designs. Three of the field’s leading experts guide you through systematically detecting, observing, analyzing, and rectifying both modern logic signal defects and embedded system malfunctions. The authors cover the entire life cycle of embedded system design from specification and simulation onward, illuminating key techniques and concepts with easy-to-understand illustrations. Writing for all electrical engineers, signal integrity engineers, and chip designers, the authors show how to use real-time test and measurement to address today’s increasingly difficult interoperability and compliance requirements. They also present detailed, start-to-finish case studies that walk you through commonly encountered design challenges, including ensuring that interfaces consistently operate with positive timing margins without incurring excessive cost; calculating total jitter budgets; and managing complex tradeoffs in high-speed serial interface design. Coverage includes Understanding the complex signal integrity issues that arise in today’s high-speed designs Learning how eye diagrams, automated compliance tests, and signal analysis measurements can help you identify and solve SI problems Reviewing the electrical characteristics of today’s most widely used CMOS IO circuits Performing signal path analyses based on intuitive Time-Domain Reflectometry (TDR) techniques Achieving more accurate real-time signal measurements and avoiding probe problems and artifacts Utilizing digital oscilloscopes and logic analyzers to make accurate measurements in high-frequency environments Simulating real-world signals that stress digital circuits and expose SI faults Accurately measuring jitter and other RF parameters in wireless applications About the Authors: Dr. Geoff Lawday is Tektronix Professor in Measurement at Buckinghamshire New University, England. He delivers courses in signal integrity engineering and high performance bus systems at the University Tektronix laboratory, and presents signal integrity seminars throughout Europe on behalf of Tektronix. David Ireland, European and Asian design and manufacturing marketing manager for Tektronix, has more than 30 years of experience in test and measurement. He writes regularly on signal integrity for leading technical journals. Greg Edlund, Senior Engineer, IBM Global Engineering Solutions division, has participated in development and testing for ten high-performance computing platforms. He authored Timing Analysis and Simulation for Signal Integrity Engineers (Prentice Hall).

With the inclusion of the two new hot topics in signal integrity, power integrity and high speed serial links, this book will be the most up to date complete guide to understanding and designing for signal integrity.

Our mission is to provide a forum for world experts to discuss technologies, address the growing needs associated with silicon technology, and exchange their discoveries and solutions for current issues of high interest. We encourage collaboration, open discussion, and critical reviews at this conference. Furthermore, we hope that this conference will also provide collaborative opportunities for those who are interested in the semiconductor industry in Asia, particularly in China.

State-of-the-art JNB and SI Problem-Solving: Theory, Analysis, Methods, and Applications Jitter, noise, and bit error (JNB) and signal integrity (SI) have become today‘s greatest challenges in high-speed digital design. Now, there’s a comprehensive and up-to-date guide to overcoming these challenges, direct from Dr. Mike Peng Li, cochair of the PCI Express jitter standard committee. One of the field’s most respected experts, Li has brought together the latest theory, analysis, methods, and practical applications, demonstrating how to solve difficult JNB and SI problems in both link components and complete systems. Li introduces the fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes. He guides readers from basic math, statistics, circuit and system models all the way through final applications. Emphasizing clock and serial data communications applications, he covers JNB and SI simulation, modeling, diagnostics, debugging, compliance testing, and much more.

The First Comprehensive, Example-Rich Guide to Power Integrity Modeling Professionals such as signal integrity engineers, package designers, and system architects need to thoroughly understand signal and power integrity issues in order to successfully design packages and boards for high speed systems. Now, for the first time, there's a complete guide to power integrity modeling: everything you need to know, from the basics through the state of the art. Using realistic case studies and downloadable software examples, two leading experts demonstrate today's best techniques for designing and modeling interconnects to efficiently distribute power and minimize noise. The authors carefully introduce the core concepts of power distribution design, systematically present and compare leading techniques for modeling noise, and link these techniques to specific applications. Their many examples range from the simplest (using analytical equations to compute power supply noise) through complex system-level applications. The authors Introduce power delivery network components, analysis, high-frequency measurement, and modeling requirements Thoroughly explain modeling of power/ground planes, including plane behavior, lumped modeling, distributed circuit-based approaches, and much more Offer in-depth coverage of simultaneous switching noise, including modeling for return currents using time- and frequency-domain analysis Introduce several leading time-domain simulation methods, such as macromodeling, and discuss their advantages and disadvantages Present the application of the modeling methods on several advanced case studies that include high-speed servers, high-speed differential signaling, chip package analysis, materials characterization, embedded decoupling capacitors, and electromagnetic bandgap structures This book's system-level focus and practical examples will make it indispensable for every student and professional concerned with power integrity, including electrical engineers, system designers, signal integrity engineers, and materials scientists. It will also be valuable to developers building software that helps to analyze high-speed systems.

New System-Level Techniques for Optimizing Signal/Power Integrity in High-Speed Interfaces--from Pioneering Innovators at Rambus, Stanford, Berkeley, and MIT As data communication rates accelerate well into the multi-gigahertz range, ensuring signal integrity both on- and off-chip has become crucial. Signal integrity can no longer be addressed solely through improvements in package or board-level design: Diverse engineering teams must work together closely from the earliest design stages to identify the best system-level solutions. In High-Speed Signaling, several of the field’s most respected practitioners and researchers introduce cutting-edge modeling, simulation, and optimization techniques for meeting this challenge. Edited by pioneering experts Drs. Dan Oh and Chuck Yuan, these contributors explain why noise and jitter are no longer separable, demonstrate how to model their increasingly complex interactions, and thoroughly introduce a new simulation methodology for predicting link-level performance with unprecedented accuracy. The authors address signal integrity from architecture through high-volume production, thoroughly discussing design, implementation, and verification. Coverage includes New advances in passive-channel modeling, power-supply noise and jitter modeling, and system margin prediction Methodologies for balancing system voltage and timing budgets to improve system robustness in high-volume manufacturing Practical, stable formulae for converting key network parameters Improved solutions for difficult problems in the broadband modeling of interconnects Equalization techniques for optimizing channel performance Important new insights into the relationships between jitter and clocking topologies New on-chip measurement techniques for in-situ link performance testing Trends and future directions in signal integrity engineering High-Speed Signaling thoroughly introduces new techniques pioneered at Rambus and other leading high-tech companies and universities: approaches that have never before been presented with this much practical detail. It will be invaluable to everyone concerned with signal integrity, including signal and power integrity engineers, high-speed I/O circuit designers, and system-level board design engineers.

iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques.

A Comprehensive Guide to Physical Layer Test and Measurement of Digital Communication Links Today's new data communication and computer interconnection systems run at unprecedented speeds, presenting new challenges not only in the design, but also in troubleshooting, test, and measurement. This book assembles contributions from practitioners at top test and measurement companies, component manufacturers,and universities. It brings together information that has never been broadly accessible before—information that was previously buried in application notes, seminar and conference presentations, short courses, and unpublished works. Readers will gain a thorough understanding of the inner workings of digital high-speed systems, and learn how the different aspects of such systems can be tested. The editors and contributors cover key areas in test and measurement of transmitters (digital waveform and jitter analysis and bit error ratio), receivers (sensitivity, jitter tolerance, and PLL/CDR characterization), and high-speed channel characterization (in time and frequency domain). Extensive illustrations are provided throughout. Coverage includes Signal integrity from a measurement point of view Digital waveform analysis using high bandwidth real-time and sampling (equivalent time) oscilloscopes Bit error ratio measurements for both electrical and optical links Extensive coverage on the topic of jitter in high-speed networks State-of-the-art optical sampling techniques for analysis of 100 Gbit/s + signals Receiver characterization: clock recovery, phase locked loops, jitter tolerance and transfer functions, sensitivity testing, and stressed-waveform receiver testing Channel and system characterization: TDR/T and frequency domain-based alternatives Testing and measuring PC architecture communication links: PCIexpress, SATA, and FB DIMM

The Number 1 VLSI Design Guide—Now Fully Updated for IP-Based Design and the Newest Technologies Modern VLSI Design, Fourth Edition, offers authoritative, up-to-the-minute guidance for the entire VLSI design process—from architecture and logic design through layout and packaging. Wayne Wolf has systematically updated his award-winning book for today’s newest technologies and highest-value design techniques. Wolf introduces powerful new IP-based design techniques at all three levels: gates, subsystems, and architecture. He presents deeper coverage of logic design fundamentals, clocking and timing, and much more. No other VLSI guide presents as much up-to-date information for maximizing performance, minimizing power utilization, and achieving rapid design turnarounds.