The lack of an integrated, compatible set of VLSI CAD tools has been suggested as a serious problem which prohibits the optimization of the academic curricula necessary to produce the required VLSI design engineers. This thesis proposes that the CAD tool problem may be solved through the development of a VLSI CAD toolkit. The characteristics of an integrated, technically complete, academically-oriented VLSI CAD toolkit have been presented. A systematic method to integrate CAD tools was developed and supported through the design of a set of CAD tool evaluation metrics. The characterization of the integrated toolkit, though not complete, appears to constitute a solid basis for future work. The evaluation metrics and methodology were simple to implement and provided absolute and relative measurements of the level of presence of desired characteristics in toolkit components. Originator-supplied key words include: CAD (Computer Aided Design), Computer program verification, Computer programs, Integrated circuits, and C language.

This book is concerned with the use of Computer-Aided Design (CAD) in the device and process development of Very-Large-Scale-Integrated Circuits (VLSI). The emphasis is in Metal-Oxide-Semiconductor (MOS) technology. State-of-the-art device and process development are presented. This book is intended as a reference for engineers involved in VLSI develop ment who have to solve many device and process problems. CAD specialists will also find this book useful since it discusses the organization of the simula tion system, and also presents many case studies where the user applies the CAD tools in different situations. This book is also intended as a text or reference for graduate students in the field of integrated circuit fabrication. Major areas of device physics and processing are described and illustrated with Simulations. The material in this book is a result of several years of work on the implemen tation of the simulation system, the refinement of physical models in the simulation programs, and the application of the programs to many cases of device developments. The text began as publications in journals and con ference proceedings, as weil as lecture notes for a Hewlett-Packard internal CAD course. This book consists of two parts. It begins with an overview of the status of CAD in VLSI, which pointsout why CAD is essential in VLSI development. Part A presents the organization of the two-dimensional simulation system.

Welcome to the proceedings of PATMOS 2008, the 18th in a series of int- national workshops. PATMOS 2008 was organized by INESC-ID / IST - TU Lisbon, Portugal, with sponsorship by Cadence, IBM, Chipidea, and Tecmic, and technical co-sponsorship by the IEEE. Over the years, PATMOS has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design meth- ologies, and tools required for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2008 c- tained state-of-the-art technical contributions, three invited talks, and a special session on recon?gurable architectures. The technical program focused on t- ing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and op- mization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 41 papers presented at PATMOS. The papers were - ganized into 7 oral sessions (with a total of 31 papers) and 2 poster sessions (with a total of 10 papers). As is customary for the PATMOS workshops, full papers were required for review, and a minimum of three reviews were received per manuscript.

This book constitutes the thoroughly refereed post-conference proceedings of 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, featuring Integrated Circuit and System Design, held in Delft, The Netherlands during September 9-11, 2009. The 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.

Welcome to the proceedings of PATMOS 2005, the 15th in a series of international workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom the IEEE Circuits and Systems Society. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the developmentof upcominggenerationsof integrated circuits and systems. The technical program of PATMOS 2005 contained state-of-the-art technical contri- tions, three invited talks, a special session on hearing-aid design, and an embedded - torial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, char- terization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert revi- ers, selected the 74 papers to be presented at PATMOS. The papers were divided into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were carried out per paper. Beyond the presentations of the papers, the PATMOS technical program was - riched by a series of speeches offered by world class experts, on important emerging research issues of industrial relevance. Prof. Jan Rabaey, Berkeley, USA, gave a talk on “Traveling the Wild Frontier of Ulta Low-Power Design”, Dr. Sung Bae Park, S- sung, gave a presentation on “DVL (Deep Low Voltage): Circuits and Devices”, Prof.