This book focuses on the design and testing of large-scale, distributed signal processing systems, with a special emphasis on systems architecture, tooling and best practices. Architecture modeling, model checking, model-based evaluation and model-based design optimization occupy central roles. Target systems with resource constraints on processing, communication or energy supply require non-trivial methodologies to model their non-functional requirements, such as timeliness, robustness, lifetime and “evolution” capacity. Besides the theoretical foundations of the methodology, an engineering process and toolchain are described. Real-world cases illustrate the theory and practice tested by the authors in the course of the European project ARTEMIS DEMANES. The book can be used as a “cookbook” for designers and practitioners working with complex embedded systems like sensor networks for the structural integrity monitoring of steel bridges, and distributed micro-climate control systems for greenhouses and smart homes.

"This book is on the topic of reconfigurable network-on-chip, which is a culmination of growing trends in the two hot research areas, namely reconfigurable computing and network-on-chip"--Provided by publisher.

As the complexity of modern embedded systems increases, it becomes less practical to design monolithic processing platforms. As a result, reconfigurable computing is being adopted widely for more flexible design. Reconfigurable Computers offer the spatial parallelism and fine-grained customizability of application-specific circuits with the postfabrication programmability of software. To make the most of this unique combination of performance and flexibility, designers need to be aware of both hardware and software issues. FPGA users must think not only about the gates needed to perform a computation but also about the software flow that supports the design process. The goal of this book is to help designers become comfortable with these issues, and thus be able to exploit the vast opportunities possible with reconfigurable logic.

The 7th IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS) followed on the success of six previous editions in Capri, Italy (2008), Santorini, Greece (2007), Gyeongju, Korea (2006), Seattle, USA (2005), Vienna, Austria (2004), and Hokodate, Japan (2003), establishing SEUS as one of the emerging workshops in the ?eld of embedded and ubiq- tous systems. SEUS 2009 continued the tradition of fostering cross-community scienti?c excellence and establishing strong links between researchand industry. The ?elds of both embedded computing and ubiquitous systems have seen considerable growth over the past few years. Given the advances in these ?elds, and also those in the areas of distributed computing, sensor networks, midd- ware, etc. , the area of ubiquitous embedded computing is now being envisioned as the wayof the future. The systems and technologies that will arise in support of ubiquitous embedded computing will undoubtedly need to address a variety of issues, including dependability, real-time, human–computer interaction, - tonomy, resource constraints, etc. All of these requirements pose a challenge to the research community. The purpose of SEUS 2009 was to bring together - searchersand practitioners with an interest in advancing the state of the artand the state of practice in this emerging ?eld, with the hope of fostering new ideas, collaborations and technologies. SEUS 2009 would not have been possible without the e?ort of many people.

Alexander Biedermann presents a generic hardware-based virtualization approach, which may transform an array of any off-the-shelf embedded processors into a multi-processor system with high execution dynamism. Based on this approach, he highlights concepts for the design of energy aware systems, self-healing systems as well as parallelized systems. For the latter, the novel so-called Agile Processing scheme is introduced by the author, which enables a seamless transition between sequential and parallel execution schemes. The design of such virtualizable systems is further aided by introduction of a dedicated design framework, which integrates into existing, commercial workflows. As a result, this book provides comprehensive design flows for the design of embedded multi-processor systems-on-chip.

This book constitutes the refereed proceedings of the 12th International Conference on Field-Programmable Logic and Applications, FPL 2002, held in Montpellier, France, in September 2002. The 104 revised regular papers and 27 poster papers presented together with three invited contributions were carefully reviewed and selected from 214 submissions. The papers are organized in topical sections on rapid prototyping, FPGA synthesis, custom computing engines, DSP applications, reconfigurable fabrics, dynamic reconfiguration, routing and placement, power estimation, synthesis issues, communication applications, new technologies, reconfigurable architectures, multimedia applications, FPGA-based arithmetic, reconfigurable processors, testing and fault-tolerance, crypto applications, multitasking, compilation techniques, etc.

This is the first book to focus on designing run-time reconfigurable systems on FPGAs, in order to gain resource and power efficiency, as well as to improve speed. Case studies in partial reconfiguration guide readers through the FPGA jungle, straight toward a working system. The discussion of partial reconfiguration is comprehensive and practical, with models introduced together with methods to implement efficiently the corresponding systems. Coverage includes concepts for partial module integration and corresponding communication architectures, floorplanning of the on-FPGA resources, physical implementation aspects starting from constraining primitive placement and routing all the way down to the bitstream required to configure the FPGA, and verification of reconfigurable systems.

"This set of books represents a detailed compendium of authoritative, research-based entries that define the contemporary state of knowledge on technology"--Provided by publisher.

Reconfigurable computing brings immense flexibility to on-chip processing while network-on-chip has improved flexibility in on-chip communication. Integrating these two areas of research reaps the benefits of both and represents the promising future of multiprocessor systems-on-chip. This book is the one of the first compilations written to demonstrate this future for network-on-chip design. Through dynamic and creative research into questions ranging from integrating reconfigurable computing techniques, to task assigning, scheduling and arrival, to designing an operating system to take advantage of the computing and communication flexibilities brought about by run-time reconfiguration and network-on-chip, it represents a complete source of the techniques and applications for reconfigurable network-on-chip necessary for understanding of future of this field.

Dynamically Reconfigurable Systems is the first ever to focus on the emerging field of Dynamically Reconfigurable Computing Systems. While programmable logic and design-time configurability are well elaborated and covered by various texts, this book presents a unique overview over the state of the art and recent results for dynamic and run-time reconfigurable computing systems. Reconfigurable hardware is not only of utmost importance for large manufacturers and vendors of microelectronic devices and systems, but also a very attractive technology for smaller and medium-sized companies. Hence, Dynamically Reconfigurable Systems also addresses researchers and engineers actively working in the field and provides them with information on the newest developments and trends in dynamic and run-time reconfigurable systems.