This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 3nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design, fabrication and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, Infineon, TSMC, etc., courseware, which, to date, has been completed by more than 7000 engineers working in a large variety of the above mentioned disciplines.

This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.

This book presents the material necessary for understanding the physics, operation, design, and performance of modern MOSFETs with nanometer dimensions. It offers a brief introduction to the field and a thorough overview of MOSFET physics, detailing the relevant basics. The authors apply presented models to calculate and demonstrate transistor characteristics, and they include required input data (e.g., dimensions, doping) enabling readers to repeat the calculations and compare their results. The book introduces conventional and novel advanced MOSFET concepts, such as multiple-gate structures or alternative channel materials. Other topics covered include high-k dielectrics and mobility enhancement techniques, MOSFETs for RF (radio frequency) applications, MOSFET fabrication technology.

This book provides readers with a broad overview of integrated circuits, also generally referred to as micro-electronics. The presentation is designed to be accessible to readers with limited, technical knowledge and coverage includes key aspects of integrated circuit design, implementation, fabrication and application. The author complements his discussion with a large number of diagrams and photographs, in order to reinforce the explanations. The book is divided into two parts, the first of which is specifically developed for people with almost no or little technical knowledge. It presents an overview of the electronic evolution and discusses the similarity between a chip floor plan and a city plan, using metaphors to help explain concepts. It includes a summary of the chip development cycle, some basic definitions and a variety of applications that use integrated circuits. The second part digs deeper into the details and is perfectly suited for professionals working in one of the semiconductor disciplines who want to broaden their semiconductor horizon.

Explains the circuit design of silicon optoelectronic integrated circuits (OEICs), which are central to advances in wireless and wired telecommunications. The essential features of optical absorption are summarized, as is the device physics of photodetectors and their integration in modern bipolar, CMOS, and BiCMOS technologies. This information provides the basis for understanding the underlying mechanisms of the OEICs described in the main part of the book. In order to cover the topic comprehensively, Silicon Optoelectronic Integrated Circuits presents detailed descriptions of many OEICs for a wide variety of applications from various optical sensors, smart sensors, 3D-cameras, and optical storage systems (DVD) to fiber receivers in deep-sub-μm CMOS. Numerous detailed illustrations help to elucidate the material.

This book presents an in-depth treatment of various power reduction and speed enhancement techniques based on multiple supply and threshold voltages. A detailed discussion of the sources of power consumption in CMOS circuits will be provided whilst focusing primarily on identifying the mechanisms by which sub-threshold and gate oxide leakage currents are generated. The authors present a comprehensive review of state-of-the-art dynamic, static supply and threshold voltage scaling techniques and discuss the pros and cons of supply and threshold voltage scaling techniques.

CMOS manufacturing environments are surrounded with symptoms that can indicate serious test, design, or reliability problems, which, in turn, can affect the financial as well as the engineering bottom line. This book educates readers, including non-engineers involved in CMOS manufacture, to identify and remedy these causes. This book instills the electronic knowledge that affects not just design but other important areas of manufacturing such as test, reliability, failure analysis, yield-quality issues, and problems. Designed specifically for the many non-electronic engineers employed in the semiconductor industry who need to reliably manufacture chips at a high rate in large quantities, this is a practical guide to how CMOS electronics work, how failures occur, and how to diagnose and avoid them. Key features: Builds a grasp of the basic electronics of CMOS integrated circuits and then leads the reader further to understand the mechanisms of failure. Unique descriptions of circuit failure mechanisms, some found previously only in research papers and others new to this publication. Targeted to the CMOS industry (or students headed there) and not a generic introduction to the broader field of electronics. Examples, exercises, and problems are provided to support the self-instruction of the reader.

本书介绍了模拟电路设计的基本概念, 说明了CMOS模拟集成电路设计技术的重要作用, 描述了MOS器件的物理模型及工作特性等.

The book all semiconductor device engineers must read to gain a practical feel for latchup-induced failure to produce lower-cost and higher-density chips. Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process. Presents real cases and solutions that occur in commercial CMOS IC chips Equips engineers with the skills to conserve chip layout area and decrease time-to-market Written by experts with real-world experience in circuit design and failure analysis Distilled from numerous courses taught by the authors in IC design houses worldwide The only book to introduce TLU under system-level ESD and EFT tests This book is essential for practicing engineers involved in IC design, IC design management, system and application design, reliability, and failure analysis. Undergraduate and postgraduate students, specializing in CMOS circuit design and layout, will find this book to be a valuable introduction to real-world industry problems and a key reference during the course of their careers.