This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.

This book covers the fundamentals and significance of 2-D materials and related semiconductor transistor technologies for the next-generation ultra low power applications. It provides comprehensive coverage on advanced low power transistors such as NCFETs, FinFETs, TFETs, and flexible transistors for future ultra low power applications owing to their better subthreshold swing and scalability. In addition, the text examines the use of field-effect transistors for biosensing applications and covers design considerations and compact modeling of advanced low power transistors such as NCFETs, FinFETs, and TFETs. TCAD simulation examples are also provided. FEATURES Discusses the latest updates in the field of ultra low power semiconductor transistors Provides both experimental and analytical solutions for TFETs and NCFETs Presents synthesis and fabrication processes for FinFETs Reviews details on 2-D materials and 2-D transistors Explores the application of FETs for biosensing in the healthcare field This book is aimed at researchers, professionals, and graduate students in electrical engineering, electronics and communication engineering, electron devices, nanoelectronics and nanotechnology, microelectronics, and solid-state circuits.

This books focuses on recent break-throughs in the development of a variety of photonic devices, serving distances ranging from mm to many km, together with their electronic counter-parts, e.g. the drivers for lasers, the amplifiers following the detectors and most important, the relevant advanced VLSI circuits. It explains that as a consequence of the increasing dominance of optical interconnects for high performance workstation clusters and supercomputers their complete design has to be revised. This book thus covers for the first time the whole variety of interdependent subjects contributing to green photonics and electronics, serving communication and energy harvesting. Alternative approaches to generate electric power using organic photovoltaic solar cells, inexpensive and again energy efficient in production are summarized. In 2015, the use of the internet consumed 5-6% of the raw electricity production in developed countries. Power consumption increases rapidly and without some transformational change will use, by the middle of the next decade at the latest, the entire electricity production. This apocalyptic outlook led to a redirection of the focus of data center and HPC developers from just increasing bit rates and capacities to energy efficiency. The high speed interconnects are all based on photonic devices. These must and can be energy efficient but they operate in an electronic environment and therefore have to be considered in a wide scope that also requires low energy electronic devices, sophisticated circuit designs and clever architectures. The development of the next generation of high performance exaFLOP computers suffers from the same problem: Their energy consumption based on present device generations is essentially prohibitive.

Robust Nano-Computing focuses on various issues of robust nano-computing, defect-tolerance design for nano-technology at different design abstraction levels. It addresses both redundancy- and configuration-based methods as well as fault detecting techniques through the development of accurate computation models and tools. The contents present an insightful view of the ongoing researches on nano-electronic devices, circuits, architectures, and design methods, as well as provide promising directions for future research.

This book covers various aspects of security, privacy and reliability in Internet of Things (IoT) and Cyber-Physical System design, analysis and testing. In particular, various established theories and practices both from academia and industry are presented and suitably organized targeting students, engineers and researchers. Fifteen leading academicians and practitioners wrote this book, pointing to the open problems and biggest challenges on which research in the near future will be focused.

The book provides a detailed analysis of issues related to sub-threshold interconnect performance from the perspective of analytical approach and design techniques. Particular emphasis is laid on the performance analysis of coupling noise and variability issues in sub-threshold domain to develop efficient compact models. The proposed analytical approach gives physical insight of the parameters affecting the transient behavior of coupled interconnects. Remedial design techniques are also suggested to mitigate the effect of coupling noise. The effects of wire width, spacing between the wires, wire length are thoroughly investigated. In addition, the effect of parameters like driver strength on peak coupling noise has also been analyzed. Process, voltage and temperature variations are prominent factors affecting sub-threshold design and have also been investigated. The process variability analysis has been carried out using parametric analysis, process corner analysis and Monte Carlo technique. The book also provides a qualitative summary of the work reported in the literature by various researchers in the design of digital sub-threshold circuits. This book should be of interest for researchers and graduate students with deeper insights into sub-threshold interconnect models in particular. In this sense, this book will best fit as a text book and/or a reference book for students who are initiated in the area of research and advanced courses in nanotechnology, interconnect design and modeling.

Increased design complexity and time-to-market pressure in the integrated circuit (IC) industry call for a raised level of abstraction at which designs are specified. High-level synthesis is the process of generating register-transfer level (RTL) implementations from behavioral specifications, and it is the key enabler for a designing at a higher level beyond RTL. As IC manufacturing technology scales down to nanoscopic scale, the synthesis tools face a number of new challenges, including complexity, power and interconnect. In this dissertation, we propose a spectrum of new techniques in high-level synthesis to address the new challenges and to improve the quality of synthesis results. 1. Efficient and versatile scheduling engine using soft constraints. We present a scheduler that distinguishes soft constraints from hard constraints when exploring the design space, and identify a class of tractable scheduling problems with soft constraints. By exploiting the total unimodularity of the constraint matrix in an integer-linear programming formulation, we are able to solve the problem optimally in polynomial time. Compared to traditional methods, the proposed approach allows easier expression of various design intentions and optimization directions, and, at the same time, gives the scheduler freedom to make global trade-offs optimally. We show that this scheduling engine is flexible enough to support a variety of design considerations in high-level synthesis. 2. Behavior-level observability analysis and power optimization. We introduce the concept of behavior-level observability and its approximations in the context of high-level synthesis, and propose an efficient procedure to compute an approximated behavior-level observability of every operation in a dataflow graph. The algorithm exploits the observability-masking nature of some Boolean operations, as well as the select operation, and treats other operations as black boxes to allow efficient word-level analysis. The result is proven to be exact under the black-box abstraction. The behavior-level observability condition obtained by our analysis can be used to optimize operation gating in the scheduler. This leads to more opportunities in subsequent RTL synthesis for power reduction. To the best of our knowledge, this is the first time behavior-level observability analysis and optimization are performed in a systematic manner. 3. Layout-friendly high-level synthesis. We study a number of structural metrics for measuring the layout-friendliness of microarchitectures generated in high-level synthesis. For a piece of connected netlist, we introduce the spreading score to measures how far components can be spread from each other with bounded wire length in a graph embedding formulation. The intuition is that components in a layout-friendly netlist (e.g., a mesh) can spread over the layout region without introducing long interconnects. Spreading score can be approximated efficiently using a semidefinite programming relaxation. Another metric based on neighborhood population is also proposed. On a number of benchmarks, spreading score shows stronger bias in favor of interconnect structures that have shorter wire length after layout, compared to previous metrics based on cut size and total multiplexer inputs.

This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts. The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs.

This book contains all the topics of importance to the low power designer. It first lays the foundation and then goes on to detail the design process. The book also discusses such special topics as power management and modal design, ultra low power, and low power design methodology and flows. In addition, coverage includes projections of the future and case studies.

Reliability concerns and the limitations of process technology can sometimes restrict the innovation process involved in designing nano-scale analog circuits. The success of nano-scale analog circuit design requires repeat experimentation, correct analysis of the device physics, process technology, and adequate use of the knowledge database. Starting with the basics, Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design introduces the essential fundamental concepts for designing analog circuits with optimal performances. This book explains the links between the physics and technology of scaled MOS transistors and the design and simulation of nano-scale analog circuits. It also explores the development of structured computer-aided design (CAD) techniques for architecture-level and circuit-level design of analog circuits. The book outlines the general trends of technology scaling with respect to device geometry, process parameters, and supply voltage. It describes models and optimization techniques, as well as the compact modeling of scaled MOS transistors for VLSI circuit simulation. • Includes two learning-based methods: the artificial neural network (ANN) and the least-squares support vector machine (LS-SVM) method • Provides case studies demonstrating the practical use of these two methods • Explores circuit sizing and specification translation tasks • Introduces the particle swarm optimization technique and provides examples of sizing analog circuits • Discusses the advanced effects of scaled MOS transistors like narrow width effects, and vertical and lateral channel engineering Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design describes the models and CAD techniques, explores the physics of MOS transistors, and considers the design challenges involving statistical variations of process technology parameters and reliability constraints related to circuit design.