This book is the proceedings volume of the 10th International Conference on Field Programmable Logic and its Applications (FPL), held August 27 30, 2000 in Villach, Austria, which covered areas like reconfigurable logic (RL), reconfigurable computing (RC), and its applications, and all other aspects. Its subtitle "The Roadmap to Reconfigurable Computing" reminds us, that we are currently witnessing the runaway of a breakthrough. The annual FPL series is the eldest international conference in the world covering configware and all its aspects. It was founded 1991 at Oxford University (UK) and is 2 years older than its two most important competitors usually taking place at Monterey and Napa. FPL has been held at Oxford, Vienna, Prague, Darmstadt, London, Tallinn, and Glasgow (also see: http://www. fpl. uni kl. de/FPL/). The New Case for Reconfigurable Platforms: Converging Media. Indicated by palmtops, smart mobile phones, many other portables, and consumer electronics, media such as voice, sound, video, TV, wireless, cable, telephone, and Internet continue to converge. This creates new opportunities and even necessities for reconfigurable platform usage. The new converged media require high volume, flexible, multi purpose, multi standard, low power products adaptable to support evolving standards, emerging new standards, field upgrades, bug fixes, and, to meet the needs of a growing number of different kinds of services offered to zillions of individual subscribers preferring different media mixes.

This book constitutes the refereed proceedings of the 12th International Conference on Field-Programmable Logic and Applications, FPL 2002, held in Montpellier, France, in September 2002. The 104 revised regular papers and 27 poster papers presented together with three invited contributions were carefully reviewed and selected from 214 submissions. The papers are organized in topical sections on rapid prototyping, FPGA synthesis, custom computing engines, DSP applications, reconfigurable fabrics, dynamic reconfiguration, routing and placement, power estimation, synthesis issues, communication applications, new technologies, reconfigurable architectures, multimedia applications, FPGA-based arithmetic, reconfigurable processors, testing and fault-tolerance, crypto applications, multitasking, compilation techniques, etc.

This book constitutes the refereed proceedings of the 14th International Conference on Field-Programmable Logic, FPL 2003, held in Leuven, Belgium in August/September 2004. The 78 revised full papers, 45 revised short papers, and 29 poster abstracts presented together with 3 keynote contributions and 3 tutorial summaries were carefully reviewed and selected from 285 papers submitted. The papers are organized in topical sections on organic and biologic computing, security and cryptography, platform-based design, algorithms and architectures, acceleration application, architecture, physical design, arithmetic, multitasking, circuit technology, network processing, testing, applications, signal processing, computational models and compiler, dynamic reconfiguration, networks and optimisation algorithms, system-on-chip, high-speed design, image processing, network-on-chip, power-aware design, IP-based design, co-processing architectures, system level design, physical interconnect, computational models, cryptography and compression, network applications and architecture, and debugging and test.

This book constitutes the refereed proceedings of the 13th International Conference on Field-Programmable Logic and Applications, FPL 2003, held in Lisbon, Portugal in September 2003. The 90 revised full papers and 56 revised poster papers presented were carefully reviewed and selected from 216 submissions. The papers are organized in topical sections on technologies and trends, communications applications, high level design tools, reconfigurable architecture, cryptographic applications, multi-context FPGAs, low-power issues, run-time reconfiguration, compilation tools, asynchronous techniques, bio-related applications, codesign, reconfigurable fabrics, image processing applications, SAT techniques, application-specific architectures, DSP applications, dynamic reconfiguration, SoC architectures, emulation, cache design, arithmetic, bio-inspired design, SoC design, cellular applications, fault analysis, and network applications.

Fine- and Coarse-Grain Reconfigurable Computing gives the basic concepts and building blocks for the design of Fine- (or FPGA) and Coarse-Grain Reconfigurable Architectures. Recently-developed integrated architecture design and software-supported design flow of FPGA and coarse-grain reconfigurable architecture are also described. Part I consists of two extensive surveys of FPGA and Coarse-Grain Reconfigurable Architectures. In Part II, case studies, innovative research results about reconfigurable architectures and design frameworks from three projects AMDREL, MOLEN and ADRES and DRESC, and, a new classification according to microcoded architectural criteria are described. Fine- and Coarse-Grain Reconfigurable Computing is an essential reference for researchers and professionals and can be used as a textbook by undergraduate, graduate students and professors.

This book is the proceedings volume of the 10th International Conference on Field Programmable Logic and its Applications (FPL), held August 27 30, 2000 in Villach, Austria, which covered areas like reconfigurable logic (RL), reconfigurable computing (RC), and its applications, and all other aspects. Its subtitle "The Roadmap to Reconfigurable Computing" reminds us, that we are currently witnessing the runaway of a breakthrough. The annual FPL series is the eldest international conference in the world covering configware and all its aspects. It was founded 1991 at Oxford University (UK) and is 2 years older than its two most important competitors usually taking place at Monterey and Napa. FPL has been held at Oxford, Vienna, Prague, Darmstadt, London, Tallinn, and Glasgow (also see: http://www. fpl. uni kl. de/FPL/). The New Case for Reconfigurable Platforms: Converging Media. Indicated by palmtops, smart mobile phones, many other portables, and consumer electronics, media such as voice, sound, video, TV, wireless, cable, telephone, and Internet continue to converge. This creates new opportunities and even necessities for reconfigurable platform usage. The new converged media require high volume, flexible, multi purpose, multi standard, low power products adaptable to support evolving standards, emerging new standards, field upgrades, bug fixes, and, to meet the needs of a growing number of different kinds of services offered to zillions of individual subscribers preferring different media mixes.

The relevance of the Internet has dramatically grown in the past decades. However, the enormous financial impact attracts many types of criminals. Setting up proper security mechanisms (e.g., Intrusion Detection Systems (IDS)) has therefore never been more important than today. To further compete with today's data transfer rates (10 to 100 Gbit/s), dedicated hardware accelerators have been proposed to offload compute intensive tasks from general purpose processors. As one key technology, reconfigurable hardware architectures, e.g., the Field Programmable Gate Array (FPGA), are of particular interest to this end. This work addresses the use of such FPGAs in the context of interactive communication applications, which goes beyond the regular packet level operations often seen in this area. To support rapid prototyping, a novel FPGA platform (NetStage) has been designed and developed, which provides a communication core for Internet communication and a flexible connection bus for attaching custom applications modules. A hardware honeypot (the MalCoBox) has been set up as a proof-of-concept application. Furthermore, to address the ongoing issue of hardware programming complexity, the domain-specific Malacoda language for abstractly formulating honeypot packet communication dialogs is presented and discussed. An associated compiler translates Malacoda into high-performance hardware modules for NetStage. Together, NetStage and Malacoda address some of the productivity deficiencies often recognized as major hindrances for the more widespread use of reconfigurable computing in communications applications. Finally, the NetStage platform has been evaluated in a real production environment.

Reconfigurable systems have pervaded nearly all fields of computation and will continue to do so for the foreseeable future. Reconfigurable System Design and Verification provides a compendium of design and verification techniques for reconfigurable systems, allowing you to quickly search for a technique and determine if it is appropriate to the task at hand. It bridges the gap between the need for reconfigurable computing education and the burgeoning development of numerous different techniques in the design and verification of reconfigurable systems in various application domains. The text explains topics in such a way that they can be immediately grasped and put into practice. It starts with an overview of reconfigurable computing architectures and platforms and demonstrates how to develop reconfigurable systems. This sets up the discussion of the hardware, software, and system techniques that form the core of the text. The authors classify design and verification techniques into primary and secondary categories, allowing the appropriate ones to be easily located and compared. The techniques discussed range from system modeling and system-level design to co-simulation and formal verification. Case studies illustrating real-world applications, detailed explanations of complex algorithms, and self-explaining illustrations add depth to the presentation. Comprehensively covering all techniques related to the hardware-software design and verification of reconfigurable systems, this book provides a single source for information that otherwise would have been dispersed among the literature, making it very difficult to search, compare, and select the technique most suitable. The authors do it all for you, making it easy to find the techniques that fit your system requirements, without having to surf the net or digital libraries to find the candidate techniques and compare them yourself.

As embedded systems become more complex, designers face a number of challenges at different levels: they need to boost performance, while keeping energy consumption as low as possible, they need to reuse existent software code, and at the same time they need to take advantage of the extra logic available in the chip, represented by multiple processors working together. This book describes several strategies to achieve such different and interrelated goals, by the use of adaptability. Coverage includes reconfigurable systems, dynamic optimization techniques such as binary translation and trace reuse, new memory architectures including homogeneous and heterogeneous multiprocessor systems, communication issues and NOCs, fault tolerance against fabrication defects and soft errors, and finally, how one can combine several of these techniques together to achieve higher levels of performance and adaptability. The discussion also includes how to employ specialized software to improve this new adaptive system, and how this new kind of software must be designed and programmed.