This book explores the design implications of emerging, non-volatile memory (NVM) technologies on future computer memory hierarchy architecture designs. Since NVM technologies combine the speed of SRAM, the density of DRAM, and the non-volatility of Flash memory, they are very attractive as the basis for future universal memories. This book provides a holistic perspective on the topic, covering modeling, design, architecture and applications. The practical information included in this book will enable designers to exploit emerging memory technologies to improve significantly the performance/power/reliability of future, mainstream integrated circuits.

This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc. The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the “memory wall.” The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification; hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named “Moguls” is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs.

As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveying the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions to enable PCM for main memories. Finally, the authors explore the impact of such byte-addressable non-volatile memories on future storage and system designs. Table of Contents: Next Generation Memory Technologies / Architecting PCM for Main Memories / Tolerating Slow Writes in PCM / Wear Leveling for Durability / Wear Leveling Under Adversarial Settings / Error Resilience in Phase Change Memories / Storage and System Design With Emerging Non-Volatile Memories

An authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution times. It presents useful data on the relative performance of a wide spectrum of machines and offers empirical and analytical evaluations of the underlying phenomena. This book will help computer professionals appreciate the impact of caches and enable designers to maximize performance given particular implementation constraints.

This book presents the latest trends and approaches in artificial intelligence research and its application to intelligent systems. It discusses hybridization of algorithms, new trends in neural networks, optimisation algorithms and real-life issues related to the application of artificial methods. The book constitutes the second volume of the refereed proceedings of the Artificial Intelligence and Algorithms in Intelligent Systems of the 7th Computer Science On-line Conference 2018 (CSOC 2018), held online in April 2018.

Advances in Computers, Volume 118, the latest volume in this innovative series published since 1960, presents detailed coverage of new advancements in computer hardware, software, theory, design and applications. Chapters in this updated release include Introduction to non-volatile memory technologies, The emerging phase-change memory, Phase-change memory architectures, Inter-line level schemes for handling hard errors in PCMs, Handling hard errors in PCMs by using intra-line level schemes, and Addressing issues with MLC Phase-change Memory. Gives a comprehensive overlook of new memory technologies, including PCM Provides reliability features with an in-depth discussion of physical mechanisms that are currently limiting PCM capabilities Covers the work of well-known authors and researchers in the field Includes volumes that are devoted to single themes or subfields of computer science

ABSTRACT: Aggressive scaling of process technologies has allowed the semiconductor industry to keep pace with Moore's Law for the past several decades. However, CMOS process technology is approaching its limits and interconnects are becoming a major performance bottleneck. Moreover, microprocessor designers are facing an increasing number of related challenges, including high power consumption, low reliability, enlarged performance gap between high-speed processor and off-chip memory, and increased demand for high-density memory. In response to these issues, new devices and manufacturing process technologies have been proposed. Among them, three-dimensional (3D) integration is a promising technology for extending Moore's Law by stacking multiple layers of processed silicon with very high-density, low-latency, and vertical interconnects. Phase Change Memory (PCM) is another emerging technology, which is regarded as a promising candidate for the next generation of computer memory and may help solve the power and reliability challenges faced by designers. However, these emerging technologies pose unanswered questions to the field of computer architecture: What are the impacts of these emerging technologies on the microarchitecture design? How can these resources be leveraged effectively to design future processor innovatively? What new challenges are introduced and how can they is addressed?