Error Coding for Arithmetic Processors provides an understanding of arithmetically invariant codes as a primary technique of fault-tolerant computing by discussing the progress in arithmetic coding theory. The book provides an introduction to arithmetic error code, single-error detection, and long-distance codes. It also discusses algebraic structures, linear congruences, and residues. Organized into eight chapters, this volume begins with an overview of the mathematical background in number theory, algebra, and error control techniques. It then explains the basic mathematical models on a register and its number representation system. The reader is also introduced to arithmetic processors, as well as to error control techniques. The text also explores the functional units of a digital computer, including control unit, arithmetic processor, memory unit, program unit, and input/output unit. Students in advanced undergraduate or graduate level courses, researchers, and readers who are interested in applicable knowledge on arithmetic codes will find this book extremely useful.

A method of concurrent error detection for arithmetic processors is described. Low-cost residue codes with check-length l and checkbase m = 2 to the l power - 1 are described for checking arithmetic operations of addition, subtraction, multiplication, division complement, shift, and rotate. Of the three number representations, the signed-magnitude representation is preferred for residue checking. Two methods of residue generation are described: the standard method of using modulo m adders and the method of using a self-testing residue tree. A simple single-bit parity-check code is described for checking the logical operations of XOR, OR, and AND, and also the arithmetic operations of complement, shift, and rotate. For checking complement, shift, and rotate, the single-bit parity-check code is simpler to implement than the residue codes. Lim, R. S. Ames Research Center NASA-TP-1528, A-7810 RTOP 366-18-50-00-00

The IEEE Third International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP-97) will be held in Melbourne, Australia from December 8th to 12th, 1997. The purpose of this important conference is to bring together developers and researchers from universities, industry and government to advance science and technology in distributed and parallel systems and processing.