This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.

This updated printing of the leading text and reference in digital systems testing and testable design provides comprehensive, state-of-the-art coverage of the field. Included are extensive discussions of test generation, fault modeling for classic and new technologies, simulation, fault simulation, design for testability, built-in self-test, and diagnosis. Complete with numerous problems, this book is a must-have for test engineers, ASIC and system designers, and CAD developers, and advanced engineering students will find this book an invaluable tool to keep current with recent changes in the field.

An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. - Most up-to-date coverage of design for testability. - Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. - Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

How to design for optimum maintenance capabilities and minimize the repair time Design for Maintainability offers engineers a wide range of tools and techniques for incorporating maintainability into the design process for complex systems. With contributions from noted experts on the topic, the book explains how to design for optimum maintenance capabilities while simultaneously minimizing the time to repair equipment. The book contains a wealth of examples and the most up-to-date maintainability design practices that have proven to result in better system readiness, shorter downtimes, and substantial cost savings over the entire system life cycle, thereby, decreasing the Total Cost of Ownership. Design for Maintainability offers a wealth of design practices not covered in typical engineering books, thus allowing readers to think outside the box when developing maintainability design requirements. The books principles and practices can help engineers to dramatically improve their ability to compete in global markets and gain widespread customer satisfaction. This important book: Offers a complete overview of maintainability engineering as a system engineering discipline Includes contributions from authors who are recognized leaders in the field Contains real-life design examples, both good and bad, from various industries Presents realistic illustrations of good maintainability design principles Provides discussion of the interrelationships between maintainability with other related disciplines Explores trending topics in technologies Written for design and logistics engineers and managers, Design for Maintainability is a comprehensive resource containing the most reliable and innovative techniques for improving maintainability when designing a system or product.

This textbook provides a comprehensive and detailed treatment of digital systems testing and testable design. It covers thoroughly both the fundamental concepts and the latest advances in this rapidly changing field, and presents only theoretical material that supports practical applications. Successfully used worldwide, this book is an invaluable tool for test engineers, ASIC and system designers, and CAD developers.

This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces.

Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide-ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through every key area, including detailed treatment of the latest techniques such as system-on-a-chip and IDDQ testing. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.

This Textbook Provides A Comprehensive And Detailed Treatment Of Digital Systems Testing And Testable Design. It Covers Thoroughly Both The Fundamental Concepts And The Latest Advances In This Rapidly Changing Field, And Presents Only Theoretical Material That Supports Practical Applications. Successfully Used Worldwide, This Book Is An Invaluable Tool For Test Engineers, Asic And System Designers, And Cad Developers.

The Definitive, Up-to-Date Guide to Digital Design with SystemVerilog: Concepts, Techniques, and Code To design state-of-the-art digital hardware, engineers first specify functionality in a high-level Hardware Description Language (HDL)—and today’s most powerful, useful HDL is SystemVerilog, now an IEEE standard. Digital System Design with SystemVerilog is the first comprehensive introduction to both SystemVerilog and the contemporary digital hardware design techniques used with it. Building on the proven approach of his bestselling Digital System Design with VHDL, Mark Zwolinski covers everything engineers need to know to automate the entire design process with SystemVerilog—from modeling through functional simulation, synthesis, timing simulation, and verification. Zwolinski teaches through about a hundred and fifty practical examples, each with carefully detailed syntax and enough in-depth information to enable rapid hardware design and verification. All examples are available for download from the book's companion Web site, zwolinski.org. Coverage includes Using electronic design automation tools with programmable logic and ASIC technologies Essential principles of Boolean algebra and combinational logic design, with discussions of timing and hazards Core modeling techniques: combinational building blocks, buffers, decoders, encoders, multiplexers, adders, and parity checkers Sequential building blocks: latches, flip- flops, registers, counters, memory, and sequential multipliers Designing finite state machines: from ASM chart to D flip-flops, next state, and output logic Modeling interfaces and packages with SystemVerilog Designing testbenches: architecture, constrained random test generation, and assertion-based verification Describing RTL and FPGA synthesis models Understanding and implementing Design-for-Test Exploring anomalous behavior in asynchronous sequential circuits Performing Verilog-AMS and mixed-signal modeling Whatever your experience with digital design, older versions of Verilog, or VHDL, this book will help you discover SystemVerilog’s full power and use it to the fullest.