Coding Approaches to Fault Tolerance in Combinational and Dynamic Systems describes coding approaches for designing fault-tolerant systems, i.e., systems that exhibit structured redundancy that enables them to distinguish between correct and incorrect results or between valid and invalid states. Since redundancy is expensive and counter-intuitive to the traditional notion of system design, the book focuses on resource-efficient methodologies that avoid excessive use of redundancy by exploiting the algorithmic/dynamic structure of a particular combinational or dynamic system. The first part of Coding Approaches to Fault Tolerance in Combinational and Dynamic Systems focuses on fault-tolerant combinational systems providing a review of von Neumann's classical work on Probabilistic Logics (including some more recent work on noisy gates) and describing the use of arithmetic coding and algorithm-based fault-tolerant schemes in algebraic settings. The second part of the book focuses on fault tolerance in dynamic systems. Coding Approaches to Fault Tolerance in Combinational and Dynamic Systems also discusses how, in a dynamic system setting, one can relax the traditional assumption that the error-correcting mechanism is fault-free by using distributed error correcting mechanisms. The final chapter presents a methodology for fault diagnosis in discrete event systems that are described by Petri net models; coding techniques are used to quickly detect and identify failures. From the Foreword: "Hadjicostis has significantly expanded the setting to processes occurring in more general algebraic and dynamic systems... The book responds to the growing need to handle faults in complex digital chips and complex networked systems, and to consider the effects of faults at the design stage rather than afterwards." George Verghese, Massachusetts Institute of Technology Coding Approaches to Fault Tolerance in Combinational and Dynamic Systems will be of interest to both researchers and practitioners in the area of fault tolerance, systems design and control.

This is a comprehensive guide to fault injection techniques used to evaluate the dependability of a digital system. The description and the critical analysis of different fault injection techniques and tools are authored by key scientists in the field of system dependability and fault tolerance.

Where is system architecture heading? The special interest group on Computer and Systems Architecture (Fachausschuss Rechner- und Systemarchitektur) of the German computer and information technology associations GI and ITG a- ed this question and discussed it during two Future Workshops in 2002. The result in a nutshell: Everything will change but everything else will remain. Future systems technologies will build on a mature basis of silicon and IC technology,onwell-understoodprogramminglanguagesandsoftwareengineering techniques, and on well-established operating systems and middleware concepts. Newer and still exotic but exciting technologies like quantum computing and DNA processing are to be watched closely but they will not be mainstream in the next decade. Although there will be considerable progress in these basic technologies, is there any major trend which uni?es these diverse developments? There is a common denominator – according to the result of the two - ture Workshops – which marks a new quality. The challenge for future systems technologies lies in the mastering of complexity. Rigid and in?exible systems, built under a strict top-down regime, have reached the limits of manageable complexity, as has become obvious by the recent failure of several large-scale projects. Nature is the most complex system we know, and she has solved the problem somehow. We just haven’t understood exactly how nature does it. But it is clear that systems designed by nature, like an anthill or a beehive or a swarm of birds or a city, are di?erent from today’s technical systems that have beendesignedbyengineersandcomputerscientists.

This book constitutes the refereed proceedings of the 7th International Symposium on Self-Stabilizing Systems, SSS 2005, held in Barcelona, Spain, in October 2005. The 15 revised full papers presented were carefully reviewed and selected from 33 submissions. The papers address classical topics of self-stabilization, prevailing extensions to the field, such as snap-stabilization, code stabilization, self-stabilization with either dynamic, faulty or Byzantine components, or deal with applications of self-stabilization, either related to operating systems, security, or mobile and ad hoc networks.

After September 11th, the Department of Defense (DoD) undertook a massive and classified research project to develop new security methods using technology in order to protect secret information from terrorist attacks Written in language accessible to a general technical reader, this book examines the best methods for testing the vulnerabilities of networks and software that have been proven and tested during the past five years An intriguing introductory section explains why traditional security techniques are no longer adequate and which new methods will meet particular corporate and industry network needs Discusses software that automatically applies security technologies when it recognizes suspicious activities, as opposed to people having to trigger the deployment of those same security technologies

This text addresses the design methodologies and CAD tools available for the systematic design and design automation of analogue integrated circuits. Two complementary approaches discussed increase analogue design productivity, demonstrated throughout using design times of the different design experiments undertaken.

This volume concerns power, noise and accuracy in CMOS Analog IC Design. The authors show that power, noise and accuracy should be treated in a unitary way, as the three are inter-related. The book discusses all possible practical power-related specs at circuit and architecture level.

RF CMOS Power Amplifiers: Theory Design and Implementation focuses on the design procedure and the testing issues of CMOS RF power amplifiers. This is the first monograph addressing RF CMOS power amplifier design for emerging wireless standards. The focus on power amplifiers for short is distance wireless personal and local area networks (PAN and LAN), however the design techniques are also applicable to emerging wide area networks (WAN) infrastructure using micro or pico cell networks. The book discusses CMOS power amplifier design principles and theory and describes the architectures and tardeoffs in designing linear and nonlinear power amplifiers. It then details design examples of RF CMOS power amplifiers for short distance wireless applications (e, g., Bluetooth, WLAN) including designs for multi-standard platforms. Design aspects of RF circuits in deep submicron CMOS are also discussed. RF CMOS Power Amplifiers: Theory Design and Implementation serves as a reference for RF IC design engineers and RD and R&D managers in industry, and for graduate students conducting research in wireless semiconductor IC design in general and with CMOS technology in particular.

This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition ers from both industry and academia in the field of defect tolerance and yield en ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.