Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become one of the most popular implementation media for digital circuits and have grown into a $2 billion per year industry. As process geometries have shrunk into the deep-submicron region, the logic capacity of FPGAs has greatly increased, making FPGAs a viable implementation alternative for larger and larger designs. To make the best use of these new deep-submicron processes, one must re-design one's FPGAs and Computer- Aided Design (CAD) tools. Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes. Three factors combine to determine the performance of an FPGA: the quality of the CAD tools used to map circuits into the FPGA, the quality of the FPGA architecture, and the electrical (i.e. transistor-level) design of the FPGA. Architecture and CAD for Deep-Submicron FPGAs examines all three of these issues in concert. In order to investigate the quality of different FPGA architectures, one needs CAD tools capable of automatically implementing circuits in each FPGA architecture of interest. Once a circuit has been implemented in an FPGA architecture, one next needs accurate area and delay models to evaluate the quality (speed achieved, area required) of the circuit implementation in the FPGA architecture under test. This book therefore has three major foci: the development of a high-quality and highly flexible CAD infrastructure, the creation of accurate area and delay models for FPGAs, and the study of several important FPGA architectural issues. Architecture and CAD for Deep-Submicron FPGAs is an essential reference for researchers, professionals and students interested in FPGAs.

Low-Energy FPGAs: Architecture and Design is a primary resource for both researchers and practicing engineers in the field of digital circuit design. The book addresses the energy consumption of Field-Programmable Gate Arrays (FPGAs). FPGAs are becoming popular as embedded components in computing platforms. The programmability of the FPGA can be used to customize implementations of functions on an application basis. This leads to performance gains, and enables reuse of expensive silicon. Chapter 1 provides an overview of digital circuit design and FPGAs. Chapter 2 looks at the implication of deep-submicron technology onFPGA power dissipation. Chapter 3 describes the exploration environment to guide and evaluate design decisions. Chapter 4 discusses the architectural optimization process to evaluate the trade-offs between the flexibility of the architecture, and the effect on the performance metrics. Chapter 5 reviews different circuit techniques to reduce the performance overhead of some of the dominant components. Chapter 6 shows methods to configure FPGAs to minimize the programming overhead. Chapter 7 addresses the physical realization of some of the critical components and the final implementation of a specific low-energy FPGA. Chapter 8 compares the prototype array to an equivalent commercial architecture.

This book presents a new FPGA architecture known as tree-based FPGA architecture, due to its hierarchical nature. This type of architecture has been relatively unexplored despite their better performance and predictable routing behavior, as compared to mesh-based FPGA architectures. In this book, we explore and optimize the tree-based architecture and we evaluate it by comparing it to equivalent mesh-based FPGA architectures.

This comprehensive textbook on the field programmable gate array (FPGA) covers its history, fundamental knowledge, architectures, device technologies, computer-aided design technologies, design tools, examples of application, and future trends. Programmable logic devices represented by FPGAs have been rapidly developed in recent years and have become key electronic devices used in most IT products. This book provides both complete introductions suitable for students and beginners, and high-level techniques useful for engineers and researchers in this field. Differently developed from usual integrated circuits, the FPGA has unique structures, design methodologies, and application techniques. Allowing programming by users, the device can dramatically reduce the rising cost of development in advanced semiconductor chips. The FPGA is now driving the most advanced semiconductor processes and is an all-in-one platform combining memory, CPUs, and various peripheral interfaces. This book introduces the FPGA from various aspects for readers of different levels. Novice learners can acquire a fundamental knowledge of the FPGA, including its history, from Chapter 1; the first half of Chapter 2; and Chapter 4. Professionals who are already familiar with the device will gain a deeper understanding of the structures and design methodologies from Chapters 3 and 5. Chapters 6–8 also provide advanced techniques and cutting-edge applications and trends useful for professionals. Although the first parts are mainly suitable for students, the advanced sections of the book will be valuable for professionals in acquiring an in-depth understanding of the FPGA to maximize the performance of the device.

This book makes powerful Field Programmable Gate Array (FPGA) and reconfigurable technology accessible to software engineers by covering different state-of-the-art high-level synthesis approaches (e.g., OpenCL and several C-to-gates compilers). It introduces FPGA technology, its programming model, and how various applications can be implemented on FPGAs without going through low-level hardware design phases. Readers will get a realistic sense for problems that are suited for FPGAs and how to implement them from a software designer’s point of view. The authors demonstrate that FPGAs and their programming model reflect the needs of stream processing problems much better than traditional CPU or GPU architectures, making them well-suited for a wide variety of systems, from embedded systems performing sensor processing to large setups for Big Data number crunching. This book serves as an invaluable tool for software designers and FPGA design engineers who are interested in high design productivity through behavioural synthesis, domain-specific compilation, and FPGA overlays. Introduces FPGA technology to software developers by giving an overview of FPGA programming models and design tools, as well as various application examples; Provides a holistic analysis of the topic and enables developers to tackle the architectural needs for Big Data processing with FPGAs; Explains the reasons for the energy efficiency and performance benefits of FPGA processing; Provides a user-oriented approach and a sense for where and how to apply FPGA technology.

Programmable Logic Devices (PLDs) have become the key implementation medium for the vast majority of digital circuits designed today. While the highest-volume devices are still built with full-fabrication rather than field programmability, the trend towards ever fewer ASICs and more FPGAs is clear. This makes the field of PLD architecture ever more important, as there is stronger demand for faster, smaller, cheaper and lower-power programmable logic. PLDs are 90% routing and 10% logic. This book focuses on that 90% that is the programmable routing: the manner in which the programmable wires are connected and the circuit design of the programmable switches themselves. Anyone seeking to understand the design of an FPGA needs to become lit erate in the complexities of programmable routing architecture. This book builds on the state-of-the-art of programmable interconnect by providing new methods of investigating and measuring interconnect structures, as well as new programmable switch basic circuits. The early portion of this book provides an excellent survey of interconnec tion structures and circuits as they exist today. Lemieux and Lewis then provide a new way to design sparse crossbars as they are used in PLDs, and show that the method works with an empirical validation. This is one of a few routing architecture works that employ analytical methods to deal with the routing archi tecture design. The analysis permits interesting insights not typically possible with the standard empirical approach.

This is the first book to focus on designing run-time reconfigurable systems on FPGAs, in order to gain resource and power efficiency, as well as to improve speed. Case studies in partial reconfiguration guide readers through the FPGA jungle, straight toward a working system. The discussion of partial reconfiguration is comprehensive and practical, with models introduced together with methods to implement efficiently the corresponding systems. Coverage includes concepts for partial module integration and corresponding communication architectures, floorplanning of the on-FPGA resources, physical implementation aspects starting from constraining primitive placement and routing all the way down to the bitstream required to configure the FPGA, and verification of reconfigurable systems.

This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including those associated with many of the most common memory cores, controller IPs and system-on-chip (SoC) buses. Readers will also benefit from the author’s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain. A SoC case study is presented to compare traditional verification with the new verification methodologies. Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; Introduce a deep introduction for Verilog for both implementation and verification point of view. Demonstrates how to use IP in applications such as memory controllers and SoC buses. Describes a new verification methodology called bug localization; Presents a novel scan-chain methodology for RTL debugging; Enables readers to employ UVM methodology in straightforward, practical terms.

This book constitutes the refereed proceedings of the 11th International Conference on Field-Programmable Logic and Application, FPL 2001, held in Belfast, Northern Ireland, UK, in August 2001. The 56 revised full papers and 15 short papers presented were carefully reviewed and selected from a total of 117 submissions. The book offers topical sections on architectural framework, place and route, architecture, DSP, synthesis, encryption, runtime reconfiguration, graphics and vision, networking, processor interaction, applications, methodology, loops and systolic, image processing, faults, and arithmetic.

This little book is conceived as a service to mathematicians attending the 1998 International Congress of Mathematicians in Berlin. It presents a comprehensive, condensed overview of mathematical activity in Berlin, from Leibniz almost to the present day (without, however, including biographies of living mathematicians). Since many towering figures in mathematical history worked in Berlin, most of the chapters of this book are concise biographies. These are held together by a few survey articles presenting the overall development of entire periods of scientific life at Berlin. Overlaps between various chapters and differences in style between the chap ters were inevitable, but sometimes this provided opportunities to show different aspects of a single historical event - for instance, the Kronecker-Weierstrass con troversy. The book aims at readability rather than scholarly completeness. There are no footnotes, only references to the individual bibliographies of each chapter. Still, we do hope that the texts brought together here, and written by the various authors for this volume, constitute a solid introduction to the history of Berlin mathematics.