This comprehensive book on application-specific integrated circuits (ASICs) describes the latest methods in VLSI-systems design. ASIC design, using commercial tools and pre-designed cell libraries, is the fastest, most cost-effective, and least error-prone method of IC design. As a consequence, ASICs and ASIC-design methods have become increasingly popular in industry for a wide range of applications. The book covers both semicustom and programmable ASIC types. After describing the fundamentals of digital logic design and the physical features of each ASIC type, the book turns to ASIC logic design - design entry, logic synthesis, simulation, and test - and then to physical design - partitioning, floorplanning, placement, and routing. You will find here, in practical well-explained detail, everything you need to know to understand the design of an ASIC, and everything you must do to begin and to complete your own design. Features Broad coverage includes, in one information-packed volume, cell-based ICs, gate arrays, field-programmable gate arrays (FPGAs), and complex programmable logic devices (PLDs). Examples throughout the book have been checked with a wide range of commercial tools to ensure their accuracy and utility. Separate chapters and appendixes on both Verilog and VHDL, including material from IEEE standards, serve as a complete reference for high-level, ASIC-design entry. As in other landmark VLSI books published by Addison-Wesley - from Mead and Conway to Weste and Eshraghian - the author's teaching expertise and industry experience illuminate the presentation of useful design methods. Any engineer, manager, or student who is working with ASICs in a design project, or who is simply interested in knowing more about the different ASIC types and design styles, will find this book to be an invaluable resource, reference, and guide.

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Arranged in a format that follows the industry-common ASIC physical design flow, Physical Design Essentials begins with general concepts of an ASIC library, then examines floorplanning, placement, routing, verification, and finally, testing. Among the topics covered are Basic standard cell design, transistor-sizing, and layout styles; Linear, non-linear, and polynomial characterization; Physical design constraints and floorplanning styles; Algorithms used for placement; Clock Tree Synthesis; Parasitic extraction; Electronic Testing, and many more.

"Both inspirational and practical, ASIC Design in the Silicon Sandbox offers electronics engineers a hands-on guide to mixed-signal circuits and layouts. The book provides a detailed roadmap for designing and building custom circuits that are optimized for target devices, providing enhanced functionality and lowered cost in finished products.

A new approach to the study of arithmetic circuits In Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems, the authors take a novel approach of presenting methods and examples for the synthesis of arithmetic circuits that better reflects the needs of today's computer system designers and engineers. Unlike other publications that limit discussion to arithmetic units for general-purpose computers, this text features a practical focus on embedded systems. Following an introductory chapter, the publication is divided into two parts. The first part, Mathematical Aspects and Algorithms, includes mathematical background, number representation, addition and subtraction, multiplication, division, other arithmetic operations, and operations in finite fields. The second part, Synthesis of Arithmetic Circuits, includes hardware platforms, general principles of synthesis, adders and subtractors, multipliers, dividers, and other arithmetic primitives. In addition, the publication distinguishes itself with: * A separate treatment of algorithms and circuits-a more useful presentation for both software and hardware implementations * Complete executable and synthesizable VHDL models available on the book's companion Web site, allowing readers to generate synthesizable descriptions * Proposed FPGA implementation examples, namely synthesizable low-level VHDL models for the Spartan II and Virtex families * Two chapters dedicated to finite field operations This publication is a must-have resource for students in computer science and embedded system designers, engineers, and researchers in the field of hardware and software computer system design and development. An Instructor Support FTP site is available from the Wiley editorial department.

This book provides an invaluable primer on the techniques utilized in the design of low power digital semiconductor devices. Readers will benefit from the hands-on approach which starts form the ground-up, explaining with basic examples what power is, how it is measured and how it impacts on the design process of application-specific integrated circuits (ASICs). The authors use both the Unified Power Format (UPF) and Common Power Format (CPF) to describe in detail the power intent for an ASIC and then guide readers through a variety of architectural and implementation techniques that will help meet the power intent. From analyzing system power consumption, to techniques that can be employed in a low power design, to a detailed description of two alternate standards for capturing the power directives at various phases of the design, this book is filled with information that will give ASIC designers a competitive edge in low-power design.

The tools and techniques you need to break the analog design bottleneck! Ten years ago, analog seemed to be a dead-end technology. Today, System-on-Chip (SoC) designs are increasingly mixed-signal designs. With the advent of application-specific integrated circuits (ASIC) technologies that can integrate both analog and digital functions on a single chip, analog has become more crucial than ever to the design process. Today, designers are moving beyond hand-crafted, one-transistor-at-a-time methods. They are using new circuit and physical synthesis tools to design practical analog circuits; new modeling and analysis tools to allow rapid exploration of system level alternatives; and new simulation tools to provide accurate answers for analog circuit behaviors and interactions that were considered impossible to handle only a few years ago. To give circuit designers and CAD professionals a better understanding of the history and the current state of the art in the field, this volume collects in one place the essential set of analog CAD papers that form the foundation of today's new analog design automation tools. Areas covered are: * Analog synthesis * Symbolic analysis * Analog layout * Analog modeling and analysis * Specialized analog simulation * Circuit centering and yield optimization * Circuit testing Computer-Aided Design of Analog Integrated Circuits and Systems is the cutting-edge reference that will be an invaluable resource for every semiconductor circuit designer and CAD professional who hopes to break the analog design bottleneck.

Timing, memory, power dissipation, testing, and testability are all crucial elements of VLSI circuit design. In this volume culled from the popular VLSI Handbook, experts from around the world provide in-depth discussions on these and related topics. Stacked gate, embedded, and flash memory all receive detailed treatment, including their power cons

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.*Provides numerous models and a clearly defined methodology for performing board-level simulation.*Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.