The power consumption of microprocessors is one of the most important challenges of high-performance chips and portable devices. In chapters drawn from Piguet's recently published Low-Power Electronics Design, Low-Power CMOS Circuits: Technology, Logic Design, and CAD Tools addresses the design of low-power circuitry in deep submicron technologies. It provides a focused reference for specialists involved in designing low-power circuitry, from transistors to logic gates. The book is organized into three broad sections for convenient access. The first examines the history of low-power electronics along with a look at emerging and possible future technologies. It also considers other technologies, such as nanotechnologies and optical chips, that may be useful in designing integrated circuits. The second part explains the techniques used to reduce power consumption at low levels. These include clock gating, leakage reduction, interconnecting and communication on chips, and adiabatic circuits. The final section discusses various CAD tools for designing low-power circuits. This section includes three chapters that demonstrate the tools and low-power design issues at three major companies that produce logic synthesizers. Providing detailed examinations contributed by leading experts, Low-Power CMOS Circuits: Technology, Logic Design, and CAD Tools supplies authoritative information on how to design and model for high performance with low power consumption in modern integrated circuits. It is a must-read for anyone designing modern computers or embedded systems.

This is the first book devoted to low power circuit design, and its authors have been among the first to publish papers in this area.· Low-Power CMOS VLSI Design· Physics of Power Dissipation in CMOS FET Devices· Power Estimation· Synthesis for Low Power· Design and Test of Low-Voltage CMOS Circuits· Low-Power Static Ram Architectures· Low-Energy Computing Using Energy Recovery Techniques· Software Design for Low Power

Low-Power Digital VLSI Design: Circuits and Systems addresses both process technologies and device modeling. Power dissipation in CMOS circuits, several practical circuit examples, and low-power techniques are discussed. Low-voltage issues for digital CMOS and BiCMOS circuits are emphasized. The book also provides an extensive study of advanced CMOS subsystem design. A low-power design methodology is presented with various power minimization techniques at the circuit, logic, architecture and algorithm levels. Features: Low-voltage CMOS device modeling, technology files, design rules Switching activity concept, low-power guidelines to engineering practice Pass-transistor logic families Power dissipation of I/O circuits Multi- and low-VT CMOS logic, static power reduction circuit techniques State of the art design of low-voltage BiCMOS and CMOS circuits Low-power techniques in CMOS SRAMS and DRAMS Low-power on-chip voltage down converter design Numerous advanced CMOS subsystems (e.g. adders, multipliers, data path, memories, regular structures, phase-locked loops) with several design options trading power, delay and area Low-power design methodology, power estimation techniques Power reduction techniques at the logic, architecture and algorithm levels More than 190 circuits explained at the transistor level.

This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.

This collection of important papers provides a comprehensive overview of low-power system design, from component technologies and circuits to architecture, system design, and CAD techniques. LOW POWER CMOS DESIGN summarizes the key low-power contributions through papers written by experts in this evolving field.

The book provides a comprehensive coverage of different aspects of low power circuit synthesis at various levels of design hierarchy; starting from the layout level to the system level. For a seamless understanding of the subject, basics of MOS circuits has been introduced at transistor, gate and circuit level; followed by various low-power design methodologies, such as supply voltage scaling, switched capacitance minimization techniques and leakage power minimization approaches. The content of this book will prove useful to students, researchers, as well as practicing engineers.

Low Power Design Methodologies presents the first in-depth coverage of all the layers of the design hierarchy, ranging from the technology, circuit, logic and architectural levels, up to the system layer. The book gives insight into the mechanisms of power dissipation in digital circuits and presents state of the art approaches to power reduction. Finally, it introduces a global view of low power design methodologies and how these are being captured in the latest design automation environments. The individual chapters are written by the leading researchers in the area, drawn from both industry and academia. Extensive references are included at the end of each chapter. Audience: A broad introduction for anyone interested in low power design. Can also be used as a text book for an advanced graduate class. A starting point for any aspiring researcher.

Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology. Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible. The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications.

Geared to the needs of engineers and designers in the field, this unique volume presents a remarkably detailed analysis of one of the hottest and most compelling research topics in microelectronics today - namely, low-voltage CMOS VLSI circuit techniques for VLSI systems. It features complete guidelines to diversified low-voltage and low-power circuit techniques, emphasizing the role of submicron and CMOS processing technology and device modeling in the circuit designs of low-voltage CMOS VLSI.

Designing CMOS Circuits for Low Power provides the fundamentals of low power design for logic, circuit, and physical design level as well as the "design story" of two innovative low power systems developed in the context of European Low Power Initiative for Electronic System Design. The main objective is to present in-depth analytical and design capabilities for low power design CMOS circuits. Determining the sources of power dissipation, in-depth description of the main existing low power optimization and estimation techniques, and, their corresponding advantages, drawbacks and comparisons are discussed. Part I starts with the description of the main principles of dynamic, short-circuit, static, and leakage power dissipation together with the low power strategies for reducing each power component. A typical low power design flow consists of power optimization and estimation techniques, which should be applied in each design level. Starting with the formulation of logic optimization problem, technology independent and technology-dependent power optimization steps for combinational and sequential logic circuits are presented. The power characteristics of different logic styles such as dynamic logic and pass transistor logic and alternative implementations of basic digital circuits are studied and compared in terms of performance, area and power dissipation. Efficient implementations and comparisons of adder and multiplier circuits for various topologies are addressed. Furthermore, novel techniques that reduce the power based on alternative arithmetic schemes are investigated. Then, we tackle with the power reduction techniques for SRAM and DRAM memories. In the physical design level, the power optimization issues of clock distribution, interconnect, and layout design are described. The first part ends up with the advantages and drawbacks of the simulation-based and probabilistic power estimation methods of a logic circuit. The second part gives the architecture and the design techniques used for the low power implementation of a Safety-Critical Application Specific Instruction Processor and ultrasound beamformer application specific integrated circuit. Designing CMOS Circuits for Low Power can be used as a textbook for undergraduate and graduate students, and, VLSI design engineers and professionals from academia and industry, who have had a basic knowledge of Microelectronics and CMOS digital design.