The objectives of this project were the understanding of heteroepitaxial growth of SiGe/Si, dislocation control for highly mismatched layers, and the application of such heterostructures to high speed microelectronics and optoelectronics. A new technique of dislocation control, using a low-temperature Si buffer layer, has been identified. SiGe/Si heterostructure FETs have been fabricated, using this technique. Heterostructure bipolar transistors have been utilized to realize the first SiGe-based integrated photoreceivers. The electro-optic coefficients in SiGe/Si quantum wells have also been measured. Modulators, whose operation principle is based on the small conduction band offset, in this heterostructure, has been demonstrated theoretically and experimentally, for the first time. Theoretical work, involving a charge control study of the interfacial effects in p-MOSFETs.

An interdisciplinary discussion of key materials issues and controversies in strained layer epitaxy is presented in this new volume from MRS. Research involving GeSi alloys and Si:C alloys are well represented. In the case of GeSi alloys, utilizing both strained and relaxed structures appears to be a strong component of the current research. Applications, devices and synthesis of improved relaxed and strained materials are featured. Special efforts to integrate the III-V and IV communities were also made during this symposium, and those efforts are reflected in the proceedings volume as well. Results on compositional graded layers in both the GeSi and III-V materials systems are presented. Topics include: general issues; ordering/low dimensional structures; characterization; device applications; growth of Si-based materials; and growth of compound semiconductors.

This thesis presents the SiGe source and drain (S/D) technology in the context of advanced CMOS, and addresses both device processing and epitaxy modelling. As the CMOS technology roadmap calls for continuously downscaling traditional transistor structures, controlling the parasitic effects of transistors, e.g. short channel effect, parasitic resistances and capacitances is becoming increasingly difficult. The emergence of these problems sparked a technological revolution, where a transition from planar to three-dimensional (3D) transistor design occurred in the 22nm technology node. The selective epitaxial growth (SEG) method has been used to deposit SiGe as stressor material in S/D regions to induce uniaxial strain in the channel region. The thesis investigates issues of process integration in IC production and concentrates on the key parameters of high-quality SiGe selective epitaxial growth, with a special focus on its pattern dependency behavior and on key integration issues in both 2D and 3D transistor structures, the goal being to improve future applications of SiGe SEG in advanced CMOS.

What seems routine today was not always so. The field of Si-based heterostructures rests solidly on the shoulders of materials scientists and crystal growers, those purveyors of the semiconductor “black arts” associated with the deposition of pristine films of nanoscale dimensionality onto enormous Si wafers with near infinite precision. We can now grow near-defect free, nanoscale films of Si and SiGe strained-layer epitaxy compatible with conventional high-volume silicon integrated circuit manufacturing. SiGe and Si Strained-Layer Epitaxy for Silicon Heterostructure Devices tells the materials side of the story and details the many advances in the Si-SiGe strained-layer epitaxy for device applications. Drawn from the comprehensive and well-reviewed Silicon Heterostructure Handbook, this volume defines and details the many advances in the Si/SiGe strained-layer epitaxy for device applications. Mining the talents of an international panel of experts, the book covers modern SiGe epitaxial growth techniques, epi defects and dopant diffusion in thin films, stability constraints, and electronic properties of SiGe, strained Si, and Si-C alloys. It includes appendices on topics such as the properties of Si and Ge, the generalized Moll-Ross relations, integral charge-control relations, and sample SiGe HBT compact model parameters.

An extraordinary combination of material science, manufacturing processes, and innovative thinking spurred the development of SiGe heterojunction devices that offer a wide array of functions, unprecedented levels of performance, and low manufacturing costs. While there are many books on specific aspects of Si heterostructures, the Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy is the first book to bring all aspects together in a single source. Featuring broad, comprehensive, and in-depth discussion, this handbook distills the current state of the field in areas ranging from materials to fabrication, devices, CAD, circuits, and applications. The editor includes "snapshots" of the industrial state-of-the-art for devices and circuits, presenting a novel perspective for comparing the present status with future directions in the field. With each chapter contributed by expert authors from leading industrial and research institutions worldwide, the book is unequalled not only in breadth of scope, but also in depth of coverage, timeliness of results, and authority of references. It also includes a foreword by Dr. Bernard S. Meyerson, a pioneer in SiGe technology. Containing nearly 1000 figures along with valuable appendices, the Silicon Heterostructure Handbook authoritatively surveys materials, fabrication, device physics, transistor optimization, optoelectronics components, measurement, compact modeling, circuit design, and device simulation.

Advanced semiconductor technology is depending on innovation and less on "classical" scaling. SiGe, Ge, and Related Compounds have become a key component of the arsenal in improving semiconductor performance. This issue of ECS Transactions discusses the technology to form these materials, process them, FET devices incorporating them, Surfaces and Interfaces, Optoelectronic devices, and HBT devices.