This title covers all software-related aspects of SoC design, from embedded and application-domain specific operating systems to system architecture for future SoC. It will give embedded software designers invaluable insights into the constraints imposed by the use of embedded software in an SoC context.

In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. Table of Contents: Introduction / Modeling, Simulation, and Measurement / Using Voltage and Frequency Adjustments to Manage Dynamic Power / Optimizing Capacitance and Switching Activity to Reduce Dynamic Power / Managing Static (Leakage) Power / Conclusions

This book constitutes the refereed proceedings of the 8th European Conference on Parallel Computing, Euro-Par 2002, held in Paderborn, Germany in August 2002. The 67 revised full papers and 55 research note papers presented together with 6 invited papers were carefully reviewed and selected from 265 submissions. The papers presented give a unique survey of the state of the art in parallel computing research, ranging from algorithms, software, hardware and application in various fields.

This book constitutes the thoroughly refereed post-proceedings of the 16th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2003, held in College Station, Texas, USA, in October 2003. The 35 revised full papers presented were selected from 48 submissions during two rounds of reviewing and improvement upon presentation at the workshop. The papers are organized in topical sections on adaptive optimization, data locality, parallel languages, high-level transformations, embedded systems, distributed systems software, low-level transformations, compiling for novel architectures, and optimization infrastructure.

Since its first volume in 1960, Advances in Computers has presented detailed coverage of innovations in computer hardware, software, theory, design, and applications. It has also provided contributors with a medium in which they can explore their subjects in greater depth and breadth than journal articles usually allow. As a result, many articles have become standard references that continue to be of significant, lasting value in this rapidly expanding field. - In-depth surveys and tutorials on new computer technology - Well-known authors and researchers in the field - Extensive bibliographies with most chapters - Many of the volumes are devoted to single themes or subfields of computer science

As embedded systems become more complex, designers face a number of challenges at different levels: they need to boost performance, while keeping energy consumption as low as possible, they need to reuse existent software code, and at the same time they need to take advantage of the extra logic available in the chip, represented by multiple processors working together. This book describes several strategies to achieve such different and interrelated goals, by the use of adaptability. Coverage includes reconfigurable systems, dynamic optimization techniques such as binary translation and trace reuse, new memory architectures including homogeneous and heterogeneous multiprocessor systems, communication issues and NOCs, fault tolerance against fabrication defects and soft errors, and finally, how one can combine several of these techniques together to achieve higher levels of performance and adaptability. The discussion also includes how to employ specialized software to improve this new adaptive system, and how this new kind of software must be designed and programmed.

This unique book outlines approaches to sharing and reusing resources for sustainable e-learning.

This book constitutes the thoroughly refereed post-proceedings of the Second International Workshop on Reconfigurable Computing, ARC 2006, held in Delft, The Netherlands, in March 2006. The 22 revised full papers and 35 revised short papers presented were thoroughly reviewed and selected from 95 submissions. The papers are organized in topical sections on applications, power, image processing, organization and architecture, networks and communication, security, and tools.

Based on the theme of the use of computers for supporting collaborative learning, this book includes contributions that aim to bridge both research tracks, the one focusing on interactions and the other on contents: the pedagogical use of digital portfolios, both for promoting individual reflections and for scaffolding group interactions.